Stabilizing amplifier with a programmable load line for characterization of nanodevices with negative differential resistance

Increasing research and development efforts aim to produce new types of scalable two-terminal nanodevices suitable for storing and processing information in both traditional and neuromorphic computing architectures [1, 2, 3]. Emerging devices are often based on incompletely understood mechanisms, and may exhibit strong non-linearity, negative differential resistance (NDR), oscillations, stochasticity, and memory effects. In assessing the electrical capabilities of resistive switching devices such as ReRAM[4], it is important to consider not only the device material properties but also the effects of feedback, runaway, excess electrical stresses, and the general role of the driving circuitry on measurement data.

Electrical measurements of patterned devices are inevitably carried out in the presence of resistance in series with the active material volume of the cell. This series resistance, commonly of unknown value [5, 6], may originate from a combination of the electrode leads, inactive layers of the material stack, or the triode region of a series FET current limiter. Internal and external series resistance adds current-voltage feedback to the system that affects stability and influences the operational behavior in important ways. Modification of switching speeds, threshold voltage/currents, and the range of achievable resistance states have all been observed and discussed theoretically [7, 8, 9, 10, 11, 12].

A series resistance is often intentionally placed to play the necessary role of an energy limiting mechanism, where its value can mean the difference between a functioning and non-functioning device. As an experimental technique, it is useful to be able to place different resistance values in series with the device under test (DUT) and examine the effect on switching processes. Here, the linearity of the resistive load is a convenient property for mathematical modelling; The circuit response of the simple two element series configuration (2R) is easily predictable through load line analysis in the ideal case, and is also straightforward to treat analytically in the presence of commonly encountered parasitics.

Another advantage of the 2R configuration is ease of implementation relative to integration of active FET devices on a test chip, with the latter requiring substantial fabrication cycle time. However, integrating calibrated series resistances on-chip is inflexible because each cell is attached to a single static resistance value that cannot be changed or removed. Scenarios often arise that give good reason to alter or remove the series resistance in situ. Notably, devices possessing steady states with S-type or N-type NDR each have different criteria for stable characterization, and both types are present in the SET and RESET processes of ReRAM, respectively[7]. This imposes different requirements for the series resistance value even within a single switching cycle.

Where an adjustable series resistance is required, it must be implemented externally to the wafer. The main practical challenge associated with this is that parasitic capacitance $C_{\mathrm{p}}$ at the node shared with the DUT is highly detrimental and difficult to avoid (Fig. 1). This stray capacitance slows down the dynamic response of the circuit, degrading the ability to control and to measure the voltage and current experienced by the active cell volume versus time. Coupled with rapid conductance transitions of the DUT, harmful overshoot transients are generated that strongly impact the observed switching behavior and can cause irreversible damage [13, 14, 15, 16].

While singular through-hole resistors are a common external solution, their use entails manually switching between resistance values where required. However, the stochastic nature of resistive switching cells is such that they benefit greatly from a statistical treatment using automated measurements with programmable parameters. In this work we present an external circuit design providing an adjustable linear series resistance for flexible wafer-level device characterization. The circuit, based on a digital potentiometer (digipot) chip, is remotely programmable over USB between 528 resistance levels. Importantly, the voltage signal at the low-capacitance DUT node is directly amplified for synchronous measurement with the DUT current with a bandwidth over 200 MHz. We demonstrate the circuit operation for automated characterization of NDR devices and for cycling of bipolar ReRAM cells with high speed voltage sweeps.

Applying Kirchhoff’s current law, the dynamical equation governing the time evolution of the device voltage in the circuit of Fig. 1 is

where $t$ is time and $I_{\mathrm{d}}$ in general depends on $V_{\mathrm{d}}$ and other internal state variables of the DUT. Possible steady state solutions lie on the $V_{\mathrm{d}}$-nullcline,

also known as the load line. For fast conductance switching events that are common in the targeted material systems, transient deviations from the load line occur as seen in the simplified situation of Fig. 2. During such transients, the excess energy delivered to the DUT due to capacitive discharge is significant and can strongly influence the end result of the switching process.

While the potential for overshooting transients is unavoidable in the context of a passive feedback arrangement, it is important that they are controlled to the extent possible and accurately measured when they occur. The only way that overshoots can be reduced in the discussed configuration is by minimizing the value of $C_{\mathrm{p}}$. Practically this means that a coaxial cable, acting approximately as a parasitic capacitance of 100 pF/m, cannot be used to connect $R_{\mathrm{s}}$ to the DUT. The series resistance should rather be placed as close as possible to the DUT, with the components carefully selected and the printed circuit board (PCB) layout designed for low contribution to the total $C_{\mathrm{p}}$.

High fidelity current measurements can be achieved by amplification of the voltage across a ground referenced shunt termination following transmission over a coaxial line. Using this type of current measurement, positioning the DUT (rather than $R_{s}$) adjacent to the shunt is generally preferred because it avoids low pass filtering of the $I_{\mathrm{d}}$ signal, allowing measurement of $I_{\mathrm{d}}$ at a high bandwidth that is independent of the resistance state of the device. With prior knowledge of $R_{\mathrm{s}}$, Eq. 2 is often used to calculate the $V_{\mathrm{d}}$ from a measurement of $I_{\mathrm{d}}$ and $V_{\mathrm{in}}$, but there are several drawbacks associated with this method. One is the inaccuracy that comes from neglecting the capacitive currents of the left-hand side of Eq. 1. Another problem is measurement noise introduced by the $I_{\mathrm{d}}R_{\mathrm{s}}$ term, as the small $I_{\mathrm{d}}$ signal with high relative error is multiplied by a potentially large $R_{\mathrm{s}}$ value. It is therefore advantageous to directly amplify the voltage at the DUT electrode rather than attempt to calculate it from other measured signals.

Following from these considerations, the basic intended configuration of external instruments and the designed circuit can be seen in Fig 3. If sufficient resolution is not obtained by sampling the current with a bare oscilloscope input, additional voltage amplification should be placed at the termination, where the use of several output stages is beneficial for dynamic range. Note that the length of the coaxial lines for DUT voltage and current sampling should be matched so that post-processing is not needed for signal synchronization.

A commercial integrated circuit, the DS1808 digipot from Maxim Integrated, was chosen as the central component to control the series resistance, $R_{\mathrm{s}}$. Internally it contains two separate potentiometers, each consisting of a chain of 32 resistors whose junctions can be connected to a "wiper" output via a set of CMOS transmission gates (analog switches). For each potentiometer, there are 32 available resistance settings spaced logarithmically (piecewise) from approximately $300\leavevmode\nobreak\ \Omega$ to $45\leavevmode\nobreak\ \mathrm{k\Omega}$. According to the published specifications, the DS1808 has a maximum parasitic capacitance of 10 pF and a maximum voltage range of $\pm 12$ V[17].

To increase the coverage of $R_{\mathrm{s}}$ values, the PCB is routed in a way that allows connection of both potentiometers either in series or in parallel by connecting or opening solder jumper pads. While a connection to a single potentiometer remains a possibility, the number of unique settings is increased to 528 between $600\leavevmode\nobreak\ \Omega-90\leavevmode\nobreak\ \mathrm{k}\Omega$ for the series combination and between $150\leavevmode\nobreak\ \Omega-22.5\leavevmode\nobreak\ \mathrm{k}\Omega$ for the parallel combination. Because a low resistance setting below 300 $\Omega$ is not provided by the digipots, a reed switch was also included on the PCB to add an option to short the input directly to the output.

For amplification of the output voltage, a THS3091 current-feedback operational amplifier from Texas Instruments was used in a non-inverting configuration. This device features low distortion, low noise, a bandwidth of 210 MHz, and a slew rate of $\mathrm{7300V/\upmu s}$ while adding only 0.1 pF parasitic capacitance[18].

All on-board settings are controlled via an Atmega32u4 microcontroller programmed as a USB serial interface to the PC. Control of the $R_{\mathrm{s}}$ value is accessible using any programming language able to open a serial COM connection and send a simple command composed of three integer values corresponding to the wiper positions and the state of the bypass relay. The total time from issuing a serial command to $R_{\mathrm{s}}$ reaching a new value is limited by USB / I²C communication, and is typically less than 300 $\upmu$s. The overall circuit design is visualized in the a block diagram of Fig 4, and a corresponding fabricated PCB is pictured in Fig. 5.

For quasistatic measurements of classical NDR materials using a series resistance, saddle-node bifurcations can occur that separate the NDR characteristic into stable and unstable regions. The range of the unstable region is determined by the value of the series resistor, with the bifurcations occurring where the derivative of the NDR curve voltage with respect to current crosses $-R_{\mathrm{s}}$. While sweeping voltage, sudden current jumps are observed for sufficiently low values of $R_{\mathrm{s}}$ in S-type NDR (Fig. 6A) and for sufficiently high values of $R_{\mathrm{s}}$ in N-type NDR (Fig. 6B). Thus, an adaptable $R_{\mathrm{s}}$ value allows control of the conditions under which each of these characteristic curves, which contain important information, can be measured.

Where the material mechanism of NDR is dynamic and reversible, the presence of $C_{\mathrm{p}}$ makes the measurement circuit prone to transient oscillations, and stable oscillatory limit cycles can also occur. Useful in these cases, the presented circuit is able to capture high speed transients and accurately project them onto the device $I_{\mathrm{d}},V_{\mathrm{d}}$ plane (Fig. 7). This data can be used for device modelling and circuit simulations, each relevant for example in the ongoing investigations of coupled oscillatory devices in neuromorphic systems.

In ReRAM devices, NDR behavior is mediated by a combination of Joule heating and migration of point defects in the oxide material that locally increase its conductivity[4]. Altering the $R_{\mathrm{s}}$ value allows these transitions to be probed in different ways, as seen in the example measurements of Fig. 8. In analogy to the NDR measurements of Fig. 6, a fixed value of $R_{\mathrm{s}}$ can result in sudden and unstable transitions for one or both of the SET or RESET processes. By switching the value of $R_{\mathrm{s}}$ during the measurement (Fig. 8C) it is observed that runaway load line transitions can be suppressed by appropriate selection of the external feedback.

When performing electrical measurements of resistive switching systems, the use of well understood circuitry is critical for realistic evaluation. With isolated devices vulnerable to runaway transitions, a series resistance circuit provides a simple means for control and tractable analysis of switching processes. In this context, parasitic capacitance is an important factor, and the values of both $R_{\mathrm{s}}$ and $C_{\mathrm{p}}$ lead to different switching outcomes in general. We have presented a circuit design for synchronized measurement of switching trajectories at high speed while using a programmable linear series resistance with low parasitic capacitance. Using this circuit, possible implications of the physical processes that accompany runaway transitions can be conveniently investigated, yielding insights into how optimal control can eventually be achieved.

The data that support the findings of this study are available from the corresponding author upon reasonable request.