Spiderweb array: A sparse spin-qubit array

Semiconductor quantum dots [1], particularly in silicon [2], are attractive hosts for spin qubits in large-scale quantum computation applications, because of their assumed compatibility with conventional CMOS integration processes. In addition, the $\sim 100$ nm spatial dimensions intrinsic to semiconductor spin qubits provide the potential to pack many millions of qubits inside a single quantum processor chip. The last several years have seen significant progress in spin-qubit research that resulted in the demonstration of long coherence times [3], high-fidelity single- [3, 4, 5] and two-qubit gates [6, 7], quantum algorithms [8], quantum non-demolition measurements [9, 10], and electron spin [11] and charge [12, 13] transfer.

Scaling to millions of qubits has many technological hurdles that will need to be cleared. Among them, the wiring bottleneck is a very challenging one for any solid-state qubit controlled by electrical signals [14, 15, 16]: currently at least one wire must run from the control electronics to each and every qubit, but chips have strict interconnect wiring density limitations, making a one-wire-per-qubit scheme unfeasible in the large scale. This was already an issue when classical processors started to scale up, leading to the development of techniques such as cross-bar addressing, that enabled the number of output pins $T$ to increase at a rate much slower than the number of transistor unit cells $U$ on the chip. This was formally captured by Rent’s rule: $T=c\,U^{p}$, where $c$ is the number of connections per unit cell, and $p$ is Rent’s exponent, a measure of optimization in the wiring scheme [15].

One approach to reducing Rent’s exponent in quantum-dot-based spin qubits [17, 18], involves addressing 2D quantum dot arrays of $N^{2}$ qubits using $\sim N$ word and bit lines. These cross-bar addressing schemes impose strong requirements on the homogeneity of the quantum dot potentials across the array, which in itself is a great technological hurdle. Furthermore, they are inefficient in the sense that many operations can only be executed sequentially.

A second approach is to decrease qubit density by using long-range quantum links that connect modules of qubits [14, 19]. Semiconductor spin qubits provide mechanisms to control the length-scales required for qubit-qubit interactions over a wide range, allowing to configure the desired density while still maintaining very large qubit arrays on chip. With this scheme, the distribution of the space on the chip can be customized for the integration of local, classical control electronics aimed at solving the homogeneity and operation efficiency issues.

Expanding on this potential route to solving the wiring bottleneck, we present and analyze the spiderweb array, a sparse 2D spin qubit array with single-qubit nodes separated by gate-based shuttling channels [20]. In this analogy, the qubit array resembles the open structure of a spiderweb, with vacant space between spiders (spin qubits) that move along the threads of their web (shuttling channels). We will focus on how to use the open area of the sparse array to integrate classical control electronics with quantum hardware, in order to minimize the need for off-chip interconnects, resulting in a scalable Rent’s exponent. Different from many proposal papers, we make a rather extensive initial effort to assess the feasibility of this classical-quantum integration, by considering several relevant practical aspects, without aiming or claiming to be exhaustive in this assessment. Another aim of this work is to identify immediate technological development opportunities that can be prioritized in order to operate a large-scale spiderweb array as a quantum processor.

We first describe in Sec. II the basic physical architecture of the qubit array and the implementations of the operations required to sustain the surface code. In Sec. III we describe the integration of on-chip classical electronics at different layers within the architecture. This leads to a logarithmic reduction in the number of control and measurement lines from the qubit region to the chip boundaries, which is discussed in Sec. IV. We then consider in Sec. V the footprint of the local control circuits and the array sparsity required to accommodate them. Sec. VI discusses the power dissipation in different sections of the array, assuming $\sim$1K operation [21, 22, 23], and the effects this has on the operation. Finally, we put all these ingredients together to describe a feasible implementation of a million-qubit array in Sec. VII.

The overarching concept of the spiderweb array is presented in Fig. 1. A large 2D square lattice of spin-qubits constitutes the quantum plane. The spin-qubits consist of single electrons confined in electrostatically defined quantum dots in silicon. The large 2D array of qubits can be used to implement the surface code [24], by assigning qubits as data qubits or surface code (SC-) ancilla qubits in a checkerboard fashion, and allowing single-qubit operations as well as nearest-neighbor two-qubit operations. In contrast to most other spin-qubit architectures, this array is sparse, with a qubit pitch $d$ on the order of 10 µm. This has two major implications:

1. 1.

   It facilitates the local integration of classical control electronics, consisting here of sample-and-hold circuits that provide independent DC biasing of each quantum dot gate electrode, which effectively offsets inhomogeneities in the potential landscape across the array. Consequently, the array can be considered fully homogeneous allowing the majority of qubit control signals to be shared across the entire array, which significantly reduces the number of control lines at the quantum plane boundary.

2. 2.

   It requires a means to transfer quantum information over $\sim$10-µm distances, which we implement by shuttling the qubits to operation regions–where single- and two-qubit operations are performed along with readout.

We define a unit cell as the the smallest operational set of elements, which can be concatenated with identical unit cells to form the large 2D array. This unit cell (Fig. 1(a)) contains 4 qubits, and has an area of $(2d)^{2}$ and a perimeter of $8d$. We define modules (Fig. 1(b)) consisting of $N\times N$ unit cells, with an area and a perimeter of $(2dN)^{2}$ and $8dN$, respectively. Modules define sections of the quantum plane where DC biasing and readout occur sequentially across the qubits in the module. All other operations that are part of the surface code cycle occur simultaneously in all unit cells in the entire array. Completing the array, the quantum plane (Fig. 1(c)) consists of $M\times M$ modules ($M^{2}N^{2}$ unit cells and $4M^{2}N^{2}$ qubits), covering an area and a perimeter of $(2dNM)^{2}$ and $8dNM$, respectively. As seen from Fig. 1(d), the quantum plane is designed to occupy a section of the die, with the remaining space to be used to reduce the off-chip wire count even further by adding additional on-chip electronics. Module sizes for DC biasing and readout ($N_{b}$ and $N_{r}$, respectively) may be different, as long as $N_{b}M_{b}=N_{r}M_{r}$, where $M_{b}$ and $M_{r}$ relate to the number of DC biasing modules and readout modules in the full array, respectively.

A detailed schematic of the components of a unit cell is presented in Fig. 2. The unit cell mainly consists of large linear arrays of electrostatic gates, connecting the vertices of the qubit array to the operation regions (see Fig. 2(a)). The bulk of the gates in these linear arrays make up the shuttling channels (blue gates in Fig. 2). Four phase-shifted sinusoidal signals are applied to four consecutive gates (shades of blue in Fig. 2), repeating the set of signals along the linear array to create a traveling-wave potential to trap and shuttle an electron [25, 13]. The sign of the phase difference between adjacent gates defines the shuttling direction.

Four gates at the vertices of the spiderweb array (red gates in Fig. 2(b)), are used to control both the confinement potential that keeps the electrons at the vertex while idle, as well as the tunneling in and out of the shuttling channels. The qubits are shuttled to and from the operation regions between the vertices (Fig. 2(c,d)) in order to perform single- and two-qubit operations, as well as readout and initialization. Fig. 2(c) shows a schematic of the gate structure used in the operation regions.

Single-qubit operations are performed via electric dipole spin resonance (EDSR) in a transverse magnetic field gradient provided by a pair of micromagnets [26]. Alternatively, the micromagnets can be omitted in qubit systems with large spin-orbit interaction [27]. After an electron is shuttled to the operation region and confined under the bottom red gates in Fig. 2(c), a microwave pulse is applied to the control gate labeled MW, to drive spin rotations. Qubit phase rotations can be achieved via geometric phase rotations [28] or by pulsing on the gate labeled J to temporarily detune the electron-spin energy via the Stark effect [3].

For two-qubit operations, two electrons from the vertices adjacent to the operation region are shuttled and confined under the red gates in Fig. 2(c,d), and a pulsed signal on the gate labeled J activates an exchange interaction between the two electron spins [1, 29, 30].

Most state-of-the-art spin-qubit systems use one of two spin-to-charge conversion mechanisms to read out a qubit state: 1 - spin-selective tunneling to a nearby electron reservoir (Elzerman readout) [31], or 2 - based on Pauli spin blockade (PSB readout) [2], using a second quantum dot with an ancilla electron [17, 32]. The charge state of the single or double quantum dot is then identified using a charge sensing quantum dot connected to source/drain Ohmic contacts. Although both readout techniques are compatible with this architecture, we focus here on PSB readout, due to its shorter demonstrated readout times [33, 34] and its compatibility with higher temperature operation [21, 22, 23].

PSB readout can be used to measure the parity of a spin pair [32]. If prior to the measurement, one of the qubits is prepared in a known eigenstate, the parity measurement will reveal the state of the unknown spin. Parallel spins are identified by their $(1{,}1)$ charge state while anti-parallel states are identified by their quick relaxation to the $(0{,}2)$ singlet. The singlet can be adiabatically detuned and separated into a known product state ($\ket{\uparrow\downarrow}$ or $\ket{\downarrow\uparrow}$). After this measurement protocol, the target qubit is left in its projected state and the RO-ancilla qubit remains in its original state. In the surface code protocol, the measured state of the SC-ancilla qubits can be tracked to perform the required decoding of errors. Alternatively, the target spin can be initialized after measurement by real-time feedback [14] or by letting the state thermalize to the $(0{,}2)$ singlet after every measurement, then adiabatically detuning as described above. In the spiderweb array, the target electron-spin qubit to be read out is shuttled to the operation region and confined under the bottom red gates in Fig. 2(c), alongside an ancilla electron (RO-ancilla) prepared in a known state on the neighboring dot. A PSB readout is performed to obtain a measurement of the target qubit, then the sensing dot can be tuned to store the RO-ancilla, and the two spins can be adiabatically separated with deterministic knowledge of their spin state, provided by the field gradient between the readout and sensing dot regions.

Qubits are able to share an operation region to perform single-qubit gates and only SC-ancilla qubits have to be read out. This allows to reduce the number of gates in the unit cell by reducing some operation regions to only contain the required gates to perform two-qubit gates (see Fig. 2(d)). The arrangement of qubits and operation regions shown in Fig. 2(a) constitutes a unit cell that can be tiled to obtain a fully operational surface code lattice.

Before the start of a computation, the spiderweb array needs to be initialized by loading electrons with a known spin state onto each of the qubit idling regions. This is achieved by initializing electrons in the operation regions using the two-spin thermalization and adiabatic detuning method described above, and shuttling the electrons to the nearest idling regions. Each operation region will initialize a data qubit first (discarding the second electron), followed by the SC- and RO-ancilla electrons. After these two steps, the entire array is prepared to begin the surface code cycles, which we describe below.

We have designed the unit cell in the spiderweb array such that a cyclic sequence of pulsed signals can be used to perform the required operations to sustain an efficient surface code implementation [35], with the same sequence performed in parallel across all unit cells to sustain it in an arbitrarily large array.

Fig. 3(a) shows the circuit diagram of a single surface code cycle in a unit cell (see Appendix D for details of the circuit). The circuit contains single-qubit gates denoted as $R_{\{y,z\}}(\theta)$, where $\theta$ is the angle of rotation and the subscript identifies the rotation axis on the Bloch-sphere. The two-qubit operation in the schematic is a type of phase gate $S_{p}$, decomposed as: $-iS_{p}=\sqrt{S_{w}}(R_{z}^{[1]}(\pi)\otimes I^{[2]})\sqrt{S_{w}}$, where $\sqrt{S_{w}}$ is the square-root-swap operation that is native to the exchange interaction, $I$ is the identity operator and the superscript in the single-qubit operator indicate which qubit the operation is applied to (see Appendix D for details). Each step in the circuit is implemented by shuttling the participating qubits from their idle position to the operation region to undergo the required single- or two-qubit gate, before being shuttled back to their idle position. Note that each two-qubit gate, as shown in the schematic, consists of three rounds of shuttling to achieve the required steps in the $S_{p}$ gate. Fig. 3(b) shows the required qubit shuttling scheme appropriate to each step of the surface code cycle. $R_{y}$ rotations are achieved by tuning the amplitude, phase and duration of the EDSR microwave pulse, while $R_{z}$ rotations are phase rotations achieved by using one of the methods described in Sec. II. The $\sqrt{S_{w}}$ gate is achieved by calibrating the amplitude and duration of the pulse applied to the J gate that controls the exchange interaction between the qubits (see Fig. 2(c,d)). At the end of the cycle, the SC-ancilla qubits are measured in the operation regions. The total operation time of a surface code cycle will be

where $t_{sh}$ is the time required to shuttle an electron from the vertex to the operation region and back, $t_{1q}$ is the single-qubit gate duration, $t_{sw}$ is the duration of a $\sqrt{S_{w}}$ operation and $t_{r}$ is the time required to readout the SC-ancilla qubits.

State-of-the-art surface code protocols follow one of two approaches to implementing logic gates. The first, known as defect qubits [36], requires disabling a subset of SC-ancilla qubits moving these defects around the lattice while the rounds of surface code error correction continue all around them. The process of moving the defects not only involves disabling and enabling qubits in succession, but also requires measurements on individual data qubits. The other implementation, known as lattice surgery [37], divides the array into patches, separated by an idle row of interstitial data qubits. Patches are created by splitting a section of the lattice, which requires performing a measurement of the interstitial qubits and subsequently disabling them from the surface code cycles. Patches can also be merged, by initializing the interstitial qubits and reincorporating them into the surface code cycles. The spiderweb array architecture can be designed to accommodate either type of logical qubit implementation. Patches of qubits can be disabled by preventing shuttling of a subset of qubits while the rest of the surface code operations on all remaining qubits continue. Selective qubit measurement and initialization is more complex to implement, since it will require interruptions of the regular surface code cycle.

The spiderweb array has been designed with the main intention of providing space within the qubit plane to integrate local control electronics, with the ultimate purpose of obtaining a feasible scaling factor between number of qubits and external control and measurement signals. In this section we describe in detail the implementation and function of these circuits, along with the corresponding routing of the signal lines between signal-generating source and gates, as summarized in Table 1.

The local electronic circuits described above allow for significant sharing of control lines, which results in a very efficient scaling of the ratio of the number of interconnects at the quantum plane boundary to the number of lines at the unit cell level. The line scaling factors obtained for each type of control and measurement signal are summarized in Table 3. We note that some additional interconnects will be required at the unit cell and module level in order to route connections to adjacent cells.

The sample-and-hold circuits for independent DC biasing of the gates require $O(M_{b}^{2}+N_{b})$ lines at the quantum plane boundary. Concretely, at the unit cell level, four digital address lines (green lines in Fig. 5(a)) and four enabler lines (orange lines) select a specific output of one demultiplexer, which is set to the correct voltage via a single connection to a voltage source (i.e., dcDAC) outside the quantum plane. This makes a total of 9 lines required for DC biasing. At the module level only the enabler lines scale with the number of unit cells as $4N_{b}$. Meanwhile, the 4 digital address lines and the connection to the voltage source is shared between all unit cells in a module. Every module is served by one dcDAC, so at the quantum plane level $M_{b}^{2}$ connections to dcDACs are needed, while both the digital address lines and the enabler lines are shared between all modules.

Shuttling of electrons across the array requires four signals that can be fully shared over the entire array.

Since all pulsed and microwave control signals can be shared across all unit cells in the array, a constant number of 58 of these lines (see Table 2) are required at the quantum plane boundary to sustain the surface code, irrespective of the total number of qubits.

To control the switches that disable shuttling of qubits from the idle region, we propose to use $x$ crossbars, in order to allow for $x$ qubit patches to be simultaneously created and manipulated, therefore accommodating approximately $x$ logical qubits. To obtain an estimate of $x$, we first consider that the number of physical qubits required to implement a logical qubit will depend on the maximum error correction distance $d_{c}$, measured as the number of neighboring physical qubits that can have errors before the logical qubit produces an error. The maximum number of logical qubits that will fit in the array will then depend on the chosen logical qubit implementation [40]:

where $U=M_{b}^{2}N_{b}^{2}$ is the number of unit cells in the array. In this line-counting exercise, we consider that each of the crossbars span the entire array, which require two horizontal and two vertical lines per unit cell. The number of crossbar lines then scales with $N_{b}$ and $N_{b}M_{b}$ at the module and quantum plane level, respectively. This is a worst-case estimate, since we envision that it will be good enough to define crossbars over partial sections of the array, therefore reducing the total line count. In addition, the number of lines required per crossbar for lattice surgery will likely be significantly less than for defect qubits, since only the interstitial qubits need to be locally addressed.

For the readout signals, a unit cell contains two readout SETs that both require a connection to their plunger and share a single Ohmic line. A module requires a single Ohmic line, and the plunger line scaling will depend on the multiplexing technique used. Performing $q$ sequential readouts will require $\log_{2}q$ lines to address the readout decoders. Simultaneous readout of $r$ unit cells will just require a single line that connects all the plungers together. Therefore, a readout module consisting of $N_{r}^{2}=qr$ unit cells, will require $2\log_{2}N_{r}-\log_{2}r+1$ lines in total for the readout scheme. To read out the full quantum plane, all $M_{r}^{2}$ modules require their own Ohmic line, while the address lines for the readout demultiplexers are shared.

We now consider the footprint requirements of the control electronics that need to be locally integrated in the quantum plane. This is the minimum area that needs to be available adjacent to the qubits, and therefore sets the minimum qubit pitch $d$. The most significant contribution to the footprint comes from the capacitors that are required for the sample-and-hold scheme. As summarized in Table 2, 32 gate electrodes per unit cell require a fine voltage resolution and another 32 gates require coarse resolution, which comprise a total capacitance per unit cell of $\sim$450 pF. Assuming $\sim$1 pF/µm² (using state-of-the-art deep-trench capacitor technology [42]), we estimate a total capacitor footprint $A_{c}\approx 450$ µm². In addition, we modeled a decoder circuit using 40-nm technology (see Appendix A for details) and obtained an estimate of the total footprint of the required demultiplexers $A_{d}\approx 180$ µm² per unit cell. This adds to a total footprint per unit cell of $A_{u}\approx 630$ µm², which allows to set the qubit pitch to $d\gtrsim 13$ µm. Assuming a 50-nm pitch between gate electrodes, this would require linear arrays of 260 gate electrodes per lattice arm and would set the unit cell area to $4\,d^{2}\approx 676$ µm².

The required unit cell footprint sets the qubit pitch and consequently the perimeter through which the required interconnects have to enter and leave the unit cell. To evaluate the feasibility of implementing the spiderweb array gate structure integrated with the local control electronics, we have constructed a circuit model in cadence (see Appendix B for details) with realistic parameters that includes all the essential components and connection routing scheme described here, using a total of four metal layers. To obtain an estimate of the maximum number $x_{\textrm{max,fab}}$ of crossbars that can be added for the implementation of logical qubits, we need to first estimate the maximum number of interconnect lines that can be routed across the perimeter of a unit cell $N_{\textrm{lines}}=8\,d\,N_{\textrm{layers}}/\Delta_{\textrm{i}}$, where $N_{\textrm{layers}}$ is the number of metallic layers that can be used for routing and $\Delta_{\textrm{i}}$ is the pitch of the interconnect lines. Then $x_{\textrm{max,fab}}=N_{\textrm{lines}}/8$, since each of the 4 crossbar lines will cross the unit cell perimeter twice. Assuming current numbers from the latest device roadmap report [43] $N_{\textrm{layers}}=12$ and $\Delta_{\textrm{i}}=80$ nm, we estimate $x_{\textrm{max,fab}}\approx 2000$.

As with all quantum processors that will operate at cryogenic temperatures, it is necessary to ensure that the heat dissipated during the operation is kept to within the stringent requirements set by the cooling power available [14]. In this section we will discuss some of the main sources of heat dissipation in the spiderweb array.

Routing of the signals lines across the chip requires a high-density of metallic lines at the different interconnect levels, which results in parasitic capacitances between the lines. Any oscillating or pulsed signal on these lines will dissipate energy due to the charging and discharging of these parasitic capacitances. Using the interconnect circuit model drawn in cadence as a guide, we consider the two layers with the highest line density as a regular grid of metal lines and use this to obtain an estimate of $C_{p}=700$ fF for the total parasitic capacitance of the signal lines in a unit cell (see Appendix C.1 for details). When a capacitor $C_{p}$ is charged by a voltage source $v_{p}$, the energy stored in the capacitor ($0.5C_{p}v_{p}^{2}$) is half the energy supplied by the source ($Qv_{p}=C_{p}v_{p}^{2}$). The other half is dissipated by the circuit as heat by the parasitic resistance between the voltage source and the capacitor, independent of the resistance value. This is known as the dynamic power dissipation from the parasitic capacitance and can be expressed as:

where $v_{p}$ and $f_{p}$ are the amplitude and frequency of the pulses applied to the lines. We note that this estimate includes power dissipated both by the signal lines and the driving circuit–which will be outside the quantum plane–so it should be taken as a worst case estimate.

Next, we estimate the dissipation for the sample-and-hold circuits, which comes mainly from the dynamic power consumption of the network of transistor switches driving the hold capacitors. We use the decoder model introduced in Sec. V and described in Appendix A to estimate a maximum energy dissipation of 0.35 pJ for a 4-bit decoder cycling through all 16 outputs. Using the worst-case $100$ kHz gate refresh rate previously estimated, we obtain the transient power dissipation $P_{d}<140$ nW for 4 demultiplexers in a unit cell, noting that capacitor leakage rates in state-of-the-art technologies will likely make this dissipation orders of magnitude lower. Additional capacitive-load power from charging and discharging the array of hold capacitors is negligible ($\sim$fW per unit cell).

Another important consideration is the power dissipated due to the finite resistance of lengthy lines carrying AC signals. We model the signal lines as transmission lines with finite resistance and parasitic capacitance to ground (see Appendix C.2 for details), to obtain the following expression for the power dissipation of a line running above a unit cell of length $2d=26$ $\mu$m:

where $v_{t}$ and $f_{t}$ are the amplitude and frequency of the signal, respectively.

The total power that will be dissipated by the operation of the entire array will then be

To illustrate the advantages of implementing this architecture on a large scale, let us consider a spiderweb array of $2^{20}$ ($\approx 10^{6}$) qubits, or $U=2^{18}$ unit cells.

To make a concrete assessment of the line scaling, we assume a DC biasing module size $N_{b}^{2}=1024$, with $M_{b}^{2}=256$ modules to complete the array. This sets the maximum clock frequency of the biasing demultiplexers to $f_{b}\approx 6$ GHz. We assume a measurement multiplexing strategy with $q=4$ sequential readouts of sets of 8 SC-ancilla qubits read out in parallel using amplitude, frequency and/or phase multiplexing ($r=4$). This implies a readout module size $N_{r}^{2}=16$ and $M_{r}^{2}=16384$. Omitting for the moment the crossbars required to implement logical qubits, and using the result in Table 3, the array contains a total of $c=74$ connections per unit cell and $T=16,836$ connections at the quantum plane boundary. Using the formula for Rent’s rule $T=c\,U^{p}$, we extract a Rent’s exponent $p=0.43$. Adding crossbar circuits will increase Rent’s exponent to a maximum $p=0.5$ for $x\gtrsim 200$ (see Appendix E for further discussion).

Considering that state-of-the-art qubit fidelities, require a code distance $d_{c}\approx 16$ to perform complex quantum algorithms [40], we can estimate upper bounds of $x$ from Eq. 2, $x_{\textrm{max,dq}}\approx 700$ and $x_{\textrm{max,ls}}\approx 1000$.

The total area covered by the quantum plane of this million qubit array with local control electronics, will be $(2dNM)^{2}\approx$ 177 mm². The remaining area on, for example, a 22 mm $\times$ 33 mm (726 mm²) die is $\sim$550 mm², and can be used to implement classical control circuits, i.e., among others the pulsed voltage sources we have described. In addition, additional levels of multiplexing can be employed to bring the off-chip wire count, typically being the real bottleneck for Rent’s rule, to well below the wire count at the quantum plane boundary.

We can evaluate the total duration of a surface code cycle by estimating the operation times in Eq. 1. From recent modeling of a shuttling protocol similar to the one used here [44], we estimate that with a 50 nm gate pitch we can achieve $t_{sh}\approx 50$ ns, maintaining $>$99.9% fidelity. We note that a recent experimental demonstration of this shuttling protocol [13] showed shuttling fidelities $>$90 % for distances $\sim$420 nm, an encouraging initial result towards the feasibility of this protocol at larger scales. State-of-the-art quantum dot qubit systems, with operation mechanisms similar to the ones proposed here, have demonstrated Rabi frequencies and exchange couplings $\sim$10 MHz [5, 8, 45], which correspond in our system to $t_{1q},t_{sw}\approx 25$ ns. In addition, those same systems exhibit dephasing times as long as $T_{2}^{*}\approx 20$ µs. High-fidelity readout using Pauli spin blockade has been achieved on timescales $t_{r}\approx 1$ µs [33, 34]. Assuming these operation times, we estimate an entire surface code cycle will take $t_{sc}\approx 6$ µs, more than 3$\times$ shorter than the coherence time.

Finally, we calculate the power dissipation from the sources described in Sec. VI. To estimate the power dissipated from the parasitic capacitance of the interconnects, we first note from Table 3 that the bulk of lines that need to be routed above the unit cell correspond to pulsed signals for qubit operations. These signal lines will need to be activated on average $\sim 6$ times per surface code cycle, from which we estimate $f_{p}\approx 1$ MHz. Assuming $v_{p}\approx 1$ V of pulse amplitude on these lines, we can use Eq. 4 to estimate $UP_{p}\lesssim 90$ mW for these lines. The biasing multiplexers will dissipate $UP_{d}\lesssim 40$ mW for the entire array. We use Eq. 5 to calculate the power dissipation of the lossy transmission lines carrying the higher-frequency signals. The MW signals used for single-qubit control are relatively low amplitude and pulsed with very short duty cycle, so their power dissipation will be negligible. A larger contribution will come from the lines that carry the signals for the shuttling channels, since they will be nearly continuously activated. Assuming a voltage amplitude $v_{t}=1$ V and frequency $f_{t}=1$ GHz, we estimate $UP_{t}\lesssim 0.3$ mW. These estimates suggest that the parasitic capacitance and the local demultiplexers will be the main contributors to the total power dissipation in the array, with a million-qubit spiderweb array expected to dissipate on the order of $100$ mW of power. This is well within the cooling power capabilities for 1 K operation using state-of-the-art cryogenic technologies. We can also estimate how well this power can be transferred from the chip to the cryogenic environment with currently used heat sinking techniques. Recent work [46] studying a CMOS integrated chip in a cryogenic environment (3 K) found that a circuit dissipating 200 mW increased the chip temperature by 7 K over an area of $\sim 4$ mm². Considering that the qubit plane area is 40$\times$ larger than that, we can roughly estimate $\sim 0.2$ K of self heating in the qubit plane of the spiderweb array.

The goal of this work is to provide insight into the feasibility of implementing a quantum hardware architecture with integrated local control electronics. We have shown that, with reasonable assumptions regarding quantum and classical fabrication and measurement techniques, a million qubit array made from spins in quantum dots is achievable. We have used the state-of-the-art in quantum-dot qubit development to consider a range of technical implementation aspects, and will now discuss some of the open questions that will need to be addressed based on how the technology evolves. As with most other electrically controlled solid-state qubit architectures, the distribution of high-frequency signals is not trivial, with potential issues such as standing waves and signal synchronization across the array. Some additional local circuitry will likely be needed to solve these issues.

Furthermore, qubit operation performance could be significantly improved with significant restructuring of the array topology, to place micromagnets at the qubit idle regions and add a fast gate to perform single-qubit gates. This would reduce the number of shuttles per surface code cycle, allow for dynamical decoupling during idle times to extend coherence times and correct phase errors that may arise, e.g., from the shuttling process.

If the number of cross-bars becomes the limiting factor to Rent’s exponent, it would be beneficial to move the DC-biasing and readout demultiplexers outside the quantum plane. This would reduce the footprint and in turn relax the shuttling performance requirements.

This work builds on previous large-scale qubit architectures based on quantum dots, focussing on the implementation of integrated classical and quantum electronics. We believe it will help identify the key areas of technological development required to shortcut the path towards building the future generation of quantum computers.