Spatio-Temporal Modeling for Flash Memory Channels Using Conditional Generative Nets

The basic unit of data storage in NAND flash memory is a floating-gate transistor, referred to as a cell. Today’s flash memories are capable of storing single or multiple bits (e.g. 2 to 5 bits) per cell, where the $n$-bit strings correspond to $2^{n}$ program levels. The cells are organized into an interconnected two-dimensional (2-D) array, called a block, via horizontal wordlines (WLs) and vertical bitlines (BLs). The flash memory chip is composed of a collection of such blocks. Fig. 1 depicts a schematic diagram of a planar TLC flash memory block and an example of a mapping from program levels to binary bits.

The basic unit of write (i.e., program) and read operations in flash memory is a page, corresponding to a logical bit position in a wordline of a block. On the other hand, the basic unit of an erase operation is an entire block.

To characterize the channel and create datasets for machine learning, we conducted program/erase (P/E) cycling experiments on several blocks of a commercial 1X-nm TLC flash memory chip. During each P/E cycle, the selected block is first erased, and then pseudo-random data are programmed into the successive pages in the block. At $4000$, $7000$, and $10000$ cycles, we perform read operation on the tested block. For each cell, we then the record program level and the measured voltage level. The P/E cycling experiments were performed at room temperature in a continuous manner with no wait time between the erase-program-read operations.

In the program operation, we refer to the program levels of three consecutive cells along WLs and BLs as a pattern. As an example, in Fig. 1, the programmed levels $\text{PL}_{i-1,j}\text{PL}_{i,j}\text{PL}_{i+1,j}$ in WLs $(i-1),i,(i+1)$ of BL $j$, correspond to bit strings “011”, “111”, “011”, which we associate with the pattern 707 in the vertical (BL) direction.

Repeated P/E operations induce wear on the flash cells, and high-low-high program levels in three consecutive cells often leads to severe ICI effects. These distortions represent the spatio-temporal nature of the flash memory channel. As a result, the level error rate increases as the temporal P/E cycle count grows, as seen in Fig. 2.

The spatial ICI effect refers to the phenomenon where programming of a cell induces changes in the voltage levels of neighboring cells within its block. In particular, the read voltage level of a cell programmed to a low level may be inadvertently increased if its adjacent cells are programmed to high levels, i.e., when the programming pattern is high-low-high. For example, if we program a 707 pattern in a TLC flash memory, the read voltage of the low central cell may be increased by its high adjacent cells. During data detection, the recovered program level of the central “victim” cell may therefore be erroneously interpreted as an incorrect level. These the severe ICI effects can be observed in Fig. 2. At each P/E cycle, we see that the cell errors are not randomly distributed; they are clearly affected by neighboring program levels. The 9 patterns shown are the most error-prone in both WL and BL directions. Pattern 707 in the BL direction is the most severely affected by ICI. Moreover, patterns 707, 706, and 607 in the BL direction are more error-prone than those on the WL direction.

We note that, to mitigate the effects of ICI in flash memory, the use of constrained codes that prevent the appearance of ICI-prone patterns has been proposed; see, for example, [15, 4, 5]. Accurate modleing of the dependence of WL and BL pattern errors on the P/E cycle count can be a valuable tool to help researchers design efficient, time-aware constrained codes.

Using the P/E cycling experiment outlined in Section II-A, we collect the paired channel instances at specific P/E cycles, where the channel instances are denoted as $\{(\text{PL},\text{VL},\text{P/E})\}$. Here, we use PL, VL, and P/E to denote the input program level of channel, the output voltage level of channel, and the P/E cycle count, respectively. The goal of channel reconstruction and generative modeling in this paper is to learn the analytically intractable likelihood $P(\text{VL}|\text{PL},\text{P/E})$, with the aim of capturing the spatio-temporal nature of the flash memory channel.

Fig. 3 summarizes the architecture of the generative modeling pipeline. The conditional VAE-GAN architecture consists of three components: an encoder ($Enc$), a generator ($Gen$), and a discriminator ($Dis$). The encoder maps the read voltages to the latent vector $z$ at a specific P/E and replaces the prior distribution $P(z)$ in the GAN with the learned posterior distribution $P(z|\text{VL},\text{P/E})$. The decoder in the VAE shares its weights with the GAN generator [3]. In the conditional setting, the variational lower bound of $P(\text{VL}|\text{P/E})$ can be derived as

Aiming to capture the spatial ICI effects in the channel model, we implement the generator using a convolutional neural network (CNN) in $Gen$, where VL is reconstructed from the PL values in its cell and neighboring cells. To generate VL at an explicit P/E cycle count, we control the generator with an additional temporal factor and incorporate the explicit P/E cycle count into $Gen$.

We first encode the normalized P/E cycle count into a $d$-dimensional P/E vector, which contains expressive powers of the normalized P/E cycle, e.g., $\text{P/E}^{2}$, $\sqrt{\text{P/E}}$, etc. Then, we spatially replicate the $d$-dimensional P/E vector to the feature map with appropriate size $H\times W\times d$ and concatenate it with the $H\times W\times C$ feature from each layer in $Gen$, where $H\times W$ is the spatial dimension of the feature from each convolutional layer and $C$ is the number of channels in the CNN. The channel-wise combination produces the final feature with size $H\times W\times(C+d)$ of each layer. The fusion of the features from the program levels and the P/E feature maps guarantees the spatial-temporal characteristics of the reconstructed voltage levels.

We implement and evaluate our method using the recorded data in a commercial TLC flash chip. With the generative modeling framework, we believe this data-driven approach can be flexibly applied to flash memories of any technology generation and scale. In TLC flash memory, each block contains hundreds of pages, each of which is typically 8-16 kB in size. In order to represent the TLC flash memory without bias, we collect data from several blocks of one 1X-nm TLC chip at selected P/E cycle counts. We crop the blocks into non-overlapping $64\times 64$ 2-D arrays to formulate our paired data. The number of 2-D arrays in the training set is $1.5\times 10^{5}$ ($5\times 10^{4}$ for each P/E cycle) and the size of the evaluation dataset is $2.1\times 10^{4}$ ($7\times 10^{3}$ for each P/E cycle). The dimensions of latent vector $z$ and P/E cycle vector are both set to 6.

As we evaluate our learned model using input arrays of program levels, we collect regenerated voltage levels and count the frequency of occurrence of voltage levels over the voltage range. We then estimate the conditional PDFs of voltages associated with each program level and given P/E cycle.

Fig. 4 shows the conditional PDFs for measured data and regenerated data in the evaluation dataset at three different time stamps. The $x$-axis represents the soft read voltages spanning a certain voltage level range. The $y$-axis represents the conditional PDF. We only show conditional PDFs from program level 1 to 7 due to normalization problems of program 0; the detailed analysis of level 0 will be discussed in Section IV-B. We make two observations from Fig. 4. First, as P/E cycle count increases, the peak of the distribution in each program level drops and the distribution becomes wider. This indicates that more voltage levels exceed the read thresholds and more errors will be detected, which is consistent with the increased error rate in Fig. 2. Second, our modeled data (solid curves) almost match the measured data (triangle markers) and, thus, capture the dependence on P/E cycles.

For a more quantitative assessment, we compare our generative model with three state-of-the-art statistical models: Gaussian model [1], Normal-Laplace model [14], and Student’s t-distribution model [11]. Following the optimization process used in [11] for an MLC flash device, we fit those statistical distributions to our TLC measured distributions. We minimize the KL divergence between real distribution and fake distribution by using the Nelder-Mead simplex method  [12], where the KL divergence is denoted as $D_{KL}(P_{real},P_{fake})$. We obtain the best-fit parameters for all program levels, except $\text{PL}=0$, with each of the statistical distributions.

We then compute the level error counts under each of the distributions and quantitatively compare those fake distributions with real distributions, where the error count is a measure of the reliability and endurance of the flash memory. To calculate the level error counts from distributions, we fix 7 default read thresholds, as shown by the dash-dotted vertical lines in Fig. 4. The hard read voltages are determined by comparing soft voltages to these thresholds. For instance, if a voltage level of program level 1 lies below the first threshold or above the second threshold, the hard read level of the cell will not be designated as 1. The error probability of $\text{PL}=1$ is denoted as

where $V_{th(01)}$ denotes the voltage threshold used to distinguish between level 0 and level 1, and $V_{th(12)}$ denotes the voltage threshold used to distinguish between level 1 and level 2.

We present the level error counts for five models in the form of bar charts Fig. 5. The $x$-axis represents the chosen P/E cycle count and the label directly under each bar represents the corresponding model name. The $y$-axis corresponds to the normalized error count. At each P/E cycle count, for each model, the errors from 7 program levels are stacked as one individual bar. The stacked bar represent the total error count. For the measured distributions, we see that level 1 has the highest error counts and the total error count at 10000 P/E cycles is around 2.5$\times$ that at 4000 P/E cycles.

For the statistical distributions, we observe that the Gaussian model does not estimate the error well; this is because the tails in the actual distribution are becoming heavier as the device is cycled to severe conditions. The Normal-Laplace model, on the other hand, takes the heavier tails into consideration and provides accurate estimations of error counts at each P/E cycle. Student’s t-distribution over-estimates the errors at those P/E cycles. For the machine learning approach, cVAE-GAN slightly overestimates the wear conditions in 7000 and 10000 P/E cycles. At 4000 P/E cycles, cVAE-GAN produces more errors than the measured data. In conclusion, Normal-Laplace is the best statistical model to capture the distributions of flash devices. Our cVAE-GAN works better than Normal-Laplace at 7000 and 10000 P/E cycles but overestimate the errors at 4000 P/E cycles. (However, as shown in the next section, the generative model can not only generate realistic-looking voltage distributions but also accurately learn spatial characteristics of the read voltages.)

Overall, we conclude that cVAE-GAN can regenerate voltages as a function of P/E cycles and produce high-quality voltage levels according to visual and quantitative metrics.

As discussed in Section II-B, the read voltage of a cell may be adversely increased by ICI when the neighboring cells are programmed to high levels. Cells programmed to level 0 are the most susceptible to such ICI effects. Generating voltage levels with ICI effects is complicated due to the pattern-dependent and spatially-dependent distortions. We remark that classical statistical models focus on regeneration of the PDFs of the measured data and, as such, are not expected to be effective in capturing ICI effects.

We evaluate how well the generative model learns spatial ICI properties by examining errors associated with program level patterns $\text{PL}_{i,j-1}\;\text{PL}_{i,j}\;\text{PL}_{i,j+1}$ and $\text{PL}_{i-1,j}\;\text{PL}_{i,j}\;\text{PL}_{i+1,j}$ in the WL and BL directions, respectively. As we observed in Fig. 2, the most error-prone patterns have central victim cell as 0, i.e., $\text{PL}_{i,j}=0$. We consider pattern-dependent error probabilities in both directions. The error probability measures the relative frequency of occurrence of the WL and BL patterns when an error occurs in the victim cell. More precisely, we calculate the pattern-dependent error probabilities in WL and BL directions,

The probabilities for measured and regenerated data are visualized as pie charts in Fig. 6. When we program an interior cell to level 0, there are 64 such patterns of program levels for the pair of adjacent cells in both WL and BL directions. Without ICI effects, the errors would occur randomly for all possible patterns.

In the measured data, the 23 listed patterns account for 55% of the errors in the WL direction and around 70% of the errors in the BL direction. The dominant error pattern in both WL and BL directions is 707. Comparing the area of pattern 707 in WL and BL, we find that pattern 707 in the WL direction is less severe than that in the BL direction.

As shown in Fig. 6, for the prevalent error patterns at 7000 P/E cycles, probabilities observed in the data generated by cVAE-GAN are very similar to those seen in the measured data. The only substantial discrepancy we observed is that the generative model underestimates the fraction of the 707 pattern in the WL direction. At 4000 (resp., 10000) P/E cycles, the model underestimates (resp., overestimates) the fraction of the 707 pattern in both directions. However, at all P/E cycles, cVAE-GAN generates the same rank ordering of pattern fractions as the measured data in both directions.

These results show that cVAE-GAN generally produces spatial distributions of voltage levels in a flash memory block that capture with good accuracy the effects of ICI in both vertical and horizontal directions.