Sn/InAs Josephson junctions on selective area grown nanowires with in-situ shadowed superconductor evaporation

Nanostructures containing superconductor-semiconductor (super-semi) junctions are particularly interesting systems to study various uncommon quantum mechanical effects in electron transport. Particularly in topological physics, such hybrid systems comprising of s-wave superconductors in contact with semiconducting nanowires, have gained considerable interest in the search for the existence of Majorana modes in solid state systemsMourik et al. (2012). Simultaneously, these super-semi nanowires are important for quantum information processing for realizing gate tunable superconducting qubitsLarsen et al. (2015); De Lange et al. (2015), Cooper pair splittersBaba et al. (2018); Kürtössy et al. (2022) and quantum interference devicesHeedt et al. (2021). To enable these technologies, it is crucial to be able to fabricate high quality super-semi hybrid nanostructures.

To fabricate functional hybrid super-semi nanostructures, first, the semiconductor nanowire must contain low defect-densities to enable phase-coherent transport from one superconducting lead to the other. Growing complex networks of such nanowires can be achieved through selective area growth. Simultaneously, it is also crucial that the interface between the superconductor and semiconductor is pristine and defect-free. This is essential in creating a transparent interface which enables Andreev reflection of electrons across the normal(semiconductor)-superconductor interface to proximitize the semiconducting channel.

In past experiments, it has been demonstrated that if the growth of the nanowire and the deposition of superconductors are performed without breaking vacuum in between the steps, a sharp disorder free super-semi interface can be formed and the nanowire exhibits a clean proximitized superconducting gap without sub-gap statesChang et al. (2015); Carrad et al. (2020); Kanne et al. (2021). Deposition of superconductors shadowed by pre-patterned or grown nano-structures Heedt et al. (2021) offers flexibility in creating such superconducting junctions/islands in specific regions of the semiconducting nanowire, enabling the fabrication of complex multi-junction devices. Additionally, this technique avoids any post-growth etching of the superconductors on top of the semiconductor, which can prevent semiconductor damage from dry/wet etching processes, as well as, allow the use of a wider range of superconductors for which selective etch chemistries are unknown.

There exists only 2 reports of using shadow wall superconductor deposition on in-plane selective area grown nanowiresJung et al. (2021a); Jiang et al. (2022a). However, no extensive electrical transport characterizations were performed in these studies and most importantly, no evidence of tunable supercurrents was reported in these nanowires. In this work, we have demonstrated an integrated and highly customizable platform where superconducting tin (Sn) was deposited on selective area grown (SAG) in-plane InAs nanowires grown using chemical beam epitaxy (CBE). The Sn was deposited using angled evaporation and shadowing with pre-patterned dielectric wall structures. In particular, compared to previous works, the template fabrication method adopted in this work offers a high degree of flexibility in the height and aspect ratios of the shadow walls, and their proximities to the nanowire position. Using this technique, we demonstrated the fabrication of super(S)-normal(N)-super(S) (SNS), NS, SNSNS as well as longer chains of SNS junctions. We present transport experiments on the SNS junctions, revealing supercurrents of the order of hundreds of nanoAmperes that are tunable by gate voltages and magnetic fields. We extracted proximitized superconducting gaps of approximately $560\mu V$ in the InAs nanowire that were sizeable fractions of the bulk superconductor gap, as well as demonstrated 2e to 1e parity transitions in the SNSNS superconducting junctions. This demonstrates the feasibility of this one-shot growth and shadow-evaporation technique to fabricate Josephson junctions on in-plane SAG nanowires. In comparison to VLS nanowires, such in-plane hybrid SAG nanowires open up the possibility to explore more complex superconductor-semiconductor networks. Our work also presents the first reports of such transport measurements in the Sn-InAs nanowire hybrid system (to the best of our knowledge).

All transport measurements were performed in a dilution refrigerator at a base temperature of $\approx$ 40 mK. All the devices fabricated for this study have only two Ti/Au leads contacting the nanowires, hence we cannot perform 4 terminal measurements to eliminate line and contact resistances. Since our setup has non-linear RC filters, in order to remove their effect, we performed pseudo 4-terminal measurements by wire-bonding each Ti/Au lead to two different pads on the printed circuit board (This eliminates the line resistance but not the contact resistance). S-NW-S junctions were first measured in a DC current biasing configuration (Fig 2). From the differential resistance plot as a function of gate voltage and current bias (Fig 2(c)), we observed a gate tunable switching current $I_{sw}$. The magnitude of $I_{sw}$ decreased as the gate voltage was decreased and the electron density in the nanowire was depleted. We observed resonances above the switching current which likely arise due to multiple Andreev reflections (MARs), which are dips in resistance at constant voltage (See Supplementary Information Fig S3). The switching current exhibits a hysteresis in forward and reverse bias, possibly due to capacitiveTinkham (1996) or local heating effects Courtois et al. (2008); Paajaste et al. (2015); Günel et al. (2012); Dartiailh et al. (2021). This can be seen in the IV trace presented in Fig 2(e), at $V_{g}=0V$.

The $I_{sw}R_{n}$ product, calculated from the switching current $I_{sw}$ and the normal state resistance at high current bias $R_{n}$, is a figure of merit commonly used for characterizing Josephson junctions (Fig 2(f)). For $0V<V_{g}<1V$, this value ranged between 300-600 $\mu V$ for this device. This is a sizeable fraction of the superconducting gap of bulk tin (=600 $\mu V$ )and is comparable to previous reports in other similar systems Pendharkar et al. (2021). Some S-NW-S junctions among the devices measured demonstrated a much lower $I_{sw}R_{n}$ product (approximately 100 $\mu V$). This reduction in the $I_{sw}R_{n}$ product for some of the measured junctions could possibly be due to thermal activation leading to premature switching of the supercurrent or finite transparency of SC contacts Tinkham (1996) or disorder Khan et al. (2020).

Next, we studied the supercurrent evolution as a function of the magnetic field parallel to the nanowire (Fig 2(d)). For the device presented in Fig 2(a), we measured a critical parallel magnetic field of approximately 1 T for 15 nm thick Sn film on our nanowires. However, the critical fields of our other devices were in the range 1 - 1.8 T. This critical field value is similar to the value reported for S-NW-S junctions of the same thickness of Sn in InSb/Sn Pendharkar et al. (2021). We also observed different magnetic field dependence of the $I_{bias}$ vs axial magnetic field plots, specific to the nanowire measured and the gate voltage applied. In Fig 2(d), we see that for $B_{||}$ between $\approx\pm 0.5T$, the junction switches from the superconducting to the resistive state at roughly the same $I_{sw}$. This could be resulting from premature switching of the supercurrent due to the resonances at finite bias. Additionally, for this device, we observe kinks at $B_{||}\approx$ 0.73 T and 0.8 T that do not change with gate voltage (see Fig S4). This cannot be explained in terms of interference effects, which was previously used to explain gate tunable nodes in magnetic field dependences of supercurrent Zuo et al. (2017).

The S-NW-S device was also measured in the voltage bias configuration. Fig 3(b) shows the differential conductance $dI/dV$ as a function of the actual source-drain voltage $V_{bias}$ and the applied top gate voltage $V_{g}$. For negative gate voltages ($V_{g}<-0.675V$), the nanowire is in the pinched off regime and we see conductance peaks at finite bias due to tunneling between the superconductors. These two finite bias resonances are separated by 4$\Delta$ in $V_{bias}$, which gives an apparent superconducting gap of approximately 560 $\mu V$ - which is in good agreement with the bulk superconducting gap of Sn. This value of the apparent superconducting gap also agrees with the value for $\Delta$ obtained from tunnel spectroscopy of an NS device meausred in this study (see Fig S5(b)). For $-0.675V<V_{g}<-0.65V$, quantum dot features are observed, including Andreev bound states and supercurrent (faint zero bias peaks).

Next, we studied the axial magnetic field dependence of this device under an applied voltage bias. Fig 3(c) shows the $V_{bias}$ vs $B_{||}$ plot with the gate voltage tuned to a value in the pinched off regime ($V_{g}=-0.682V$). The gap was observed to remain open till $\approx$ 1.1 T, which is higher than the critical field obtained from the $I_{bias}$ measurement in Fig 2(d). This value is less than the critical field of 3 T reported for 15 nm thin shells of Sn Pendharkar et al. (2021), although the gap does remain open upto 3 T in $V_{bias}$ for one of our devices (Fig S6 (f)). This variation in critical field values could be due to the nucleation of Sn on InAs being different compared to InSb, resulting in grains of different thicknesses on the nanowire (thicker grains can cause the superconductivity to be suppressed). Additionally, presence of a magnetic field component perpendicular to the Sn film on the nanowire can also cause a reduction in the value of the critical magnetic field. We estimate the misalignment of the magnetic field with the nanowire axis to be $\approx\pm 10^{\circ}$. For all the S-NW-S junctions measured in this study, we observed a higher critical field in $V_{bias}$ compared to the $I_{bias}$ measurements. We speculate that at very negative gate voltages, the nanowire is in the pinched off regime, and therefore we see the superconductivity evolution of only the Sn film on the nanowire, not of the induced superconductivity in the semiconducting segment. This is in contrast to the $I_{bias}$ measurements, which were obtained at less negative gate voltages, where the nanowire was still conducting.

The shadow wall deposition technique was also used to deposit an isolated tin island as demonstrated in Fig 4. The Sn island on the InAs nanowire was coupled to source drain leads via tunnel barriers, which were modulated using the two top gates $V_{g1}$ and $V_{g2}$ (Fig 4(a) and (b)). Figs 4(d), (f) and (h) show a gate versus gate scan at an applied lockin voltage of 10 $\mu V$ (dc voltage = 0 V) at three different magnetic field values parallel to the nanowire. The peak-dip structure seen in these plots arise from the Coulomb blockade effect, with the blockade being lifted at the peaks. The periodicity was halved at very high fields (1.6 T, Fig 4(h)) compared to the zero field plot (Fig 4(d)). At zero field, if the lowest quasiparticle energy state is above the charging energy of the island, then the island prefers to host only pairs of electrons in the ground state and transport through the island happens by tunneling of Cooper pairs. As the magnetic field is increased, the quasiparticle states move down in energy. At intermediate magnetic fields ($B_{||}=1.33T$), when the quasiparticle states are below the charging energy, the island alternates between even and odd parity states as the gate voltages are varied, which manifests as different peak spacings in Fig 4(f). For very high magnetic fields ($B_{||}=1.6T$, Fig 4(h)), the island is in the normal state and single electron transport sets in leading to the 1e periodicity.

The above three situations can also be visualised in the $V_{bias}$ vs $V_{g1}$ ($V_{g2}$ = -176 mV) plots shown in Fig 4(e), (g) and (f). At $B_{||}=0T$, for small $V_{bias}$, the island shows Coulomb diamonds which are 2e periodic in the gate voltage. Above $V_{bias}=200\mu V$, the periodicity in gate voltage is halved due to the onset of single electron transport through the island (Fig 4(e)). For $B_{||}=1.33T$ (Fig 4(g)), near zero bias, a second diamond of smaller width appears between the larger diamonds due to alternating even-odd parity. At $B_{||}=1.6T$, the island transitions to the normal state and the Coulomb diamonds become 1e periodic in gate voltage (Fig 4(g)) for all $V_{bias}$. The transition from 2e to 1e charging is also evident in the gate voltage versus magnetic field plot shown in Fig 4(c). We note that the critical field for the transition is approximately 1.2 T, which is higher than the values previously reported in other hybrid semiconductor-superconductor systems Albrecht et al. (2016); Kanne et al. (2021); Shen et al. (2018); Pendharkar et al. (2021).

In conclusion, through this work we first demonstrated a process to combine selective area growth of in-plane semiconductor nanowires and angled shadow deposition to create hybrid super-semi nanostructures. We utilized this technique to fabricate and measure Sn junctions of various geometries on in-plane SAG InAs nanowires with excellent yield. Next, through cryogenic transport measurements performed on S-NW-S junctions, we demonstrated the presence of a gate-controllable supercurrent and a superconducting gap in the InAs nanowire. Further, we performed measurements on Sn islands on InAs nanowires fabricated using the same technique, which exhibit the 2e to 1e parity transition with a high critical field. These measurements show that in-plane SAG nanowires with shadow evaporated superconductor is a viable platform to probe the physics of electron transport in hybrid nanostructures.

The technique allows the fabricaton of arbitrarily high aspect ratio shadow walls, defined solely by the thickness of the deposited silicon oxide. As demonstrated in this work, these shadow walls can be situated in close proximity to the SAG nanowire trenches enabling the formation of a long superconductor shadow which can aid in shadowing larger nanowire networks. Several such shadow walls can also be used to shadow multiple materials and create interesting interfaces in a fully in-situ and epitaxial method.In the future, this work therefore presents opportunities for fabricating a wide range of more complex super-semi hybrid nanowire networks and studying their transport physics.

Full data is available at 10.5281/zenodo.7688657

The study lasted for 10 months, between January 2022 - October 2022. During this time, we fabricated 2 full 2" wafers with shadow wall templates. 5 different nanowire-superconductor growths were performed with several samples in each growth. Out of these, we fabricated two base chips. A total of nine S-NW-S junctions, six island devices and three NW-S junction on the two chips were measured over four cooldowns. Approximately 2500 data sets were collected.

Fabrication of the SAG nanowire/shadow-wall mask device on InP(001) substrates utilized 3 separate fabrication steps. In all cases, a thin aluminum oxide (AlO_x) film was first deposited via atomic layer deposition (ALD) underneath all thicker SiO₂ films deposited via plasma-enhanced chemical vapor deposition (PECVD) in order to protect the underlying substrate from plasma damage and non-volatile fluorine residues that result from the fluorine-based SiO₂ dry etches.

1.Alignment marks, etched into the InP substrate, were defined by first coating the substrate with a thin ALD AlO_x film (6nm) and a thicker PECVD SiO₂ hard mask film (30 nm). The alignment mark patterns were exposed using electron beam lithography into CSAR-62 positive resist (100 nm) and following development in MIBK/IPA solvents, the pattern was transferred into the SiO₂ hardmask using a CHF₃/CF₄/O₂ plasma in an inductively coupled plasma (ICP) etcher. This dry etch stopped in the thin AlO_x film and this film was removed by wet etching in AZ300MIF base developer which exposed the InP substrate within the mark patterns. A final dry etch step in a reactive ion etch (RIE) tool using CH₄/H₂/Ar chemistry transferred the mark patterns into the InP substrate to approximately 1$\mu$m depth. The remaining SiO_x/AlO_x films were then removed using a buffered oxide etch (BOE) and AZ300MIF dip. Note that etched alignment marks, rather than the standard metal marks, were necessary for compatibility with the later chemical beam epitaxy (CBE) growth steps.

2.Generation of the SAG nanowire trenches required redeposition of the thin ALD AlO_x (6 nm) film and PECVD SiO₂ (30 nm) film on the substrate. The trench patterns were patterned using electron beam lithography into positive CSAR-62 resist (100nm) and the trenches were etched into the SiO₂ layer using the same chemistry as in the alignment mark step above once again stopping on the protective AlO_x layer, a layer that was kept intact.

3.To fabricate the shadow-wall mask, an additional 20 nm of ALD AlO_x was deposited on the patterned substrate followed by a much thicker PECVD SiO₂ film (650 nm) and a 150 nm mask layer of Ru deposited using DC sputtering. Negative hydrogen silesquioxane (HSQ) resist was used to define the shadow-wall pattern using electron beam lithography (which was precisely positioned with respect to the nanowire trench patterns defined in the previous step using the alignment marks from the first step). After development in 25 percent tetramethyl ammonium hydroxide solution, the HSQ pattern was transferred into the Ru mask layer using O₂/Cl₂ chemistry in an ICP etcher. Ru has been shown to exhibit high selectivity in carbo-fluoro based etch chemistry and can produce near-vertical etch profiles in thick SiO₂ films Mitchell et al. (2021). Hence, the Ru pattern was used to mask the CHF₃/CF₄ ICP etch through the 650 nm thick SiO₂ film, a process which resulted in high aspect ratio shadow-walls with very narrow fingers and near-vertical sidewalls, all important requirements for the successful fabrication of the final device. Once completed, the Ru mask layer was removed by a short O₂/Cl₂ ICP etch and the remaining AlO_x protective stop layer was removed by wet etching in AZ300MIF. Note that an extended soak was required to ensure that the AlO_x was completely removed from the narrow SAG nanowire trenches.

Before loading into the CBE chamber, the patterned shadow wall SAG samples were subject to three digital oxidation/etching cycles (each cycles consists of a UV ozone oxidation step of the exposed InP surface inside the trenches immediately followed by a wet etch in dilute 1:10 HCl:H₂O solutions to remove the surface oxide). The digital etching was found to significantly improve nanowire growth yields within the narrow trenches.

For device fabrication, as mentioned in the main text, the first step is to remove Sn from around the SAG nanowire structure to avoid any shorting between the leads. For this, we defined etch windows using two separate rounds of e-beam lithography (EBL) - first, for defining small windows around the shadow walls, and then writing large patterns for etching Sn under the leads only for those nanowires where no large Sn residues were visible near the shadow junctions. Each of the above EBL steps was followed by resist development, AlO_x and Sn etching steps. For removing the AlO_x cap, we used a 1:20 CD26:DI water solution for 2 minutes, followed by two consecutive 10 seconds and 50 seconds rinses in DI water. Dilute 1:400 HCl:DI water (36.5%-38% HCl) solution under magnetic stirring was used for 15 seconds to etch Sn, followed by two rinses for 10 seconds and 50 seconds in DI water. A nitrogen jet was used for blow drying the chip after each set of etch and rinse steps. A third round of EBL was done to define the source-drain leads. After developing the resist, 10nm Ti/120 nm Au was deposited using an e-beam evaporation system. Ar ion milling was done in steps for a total of 75 seconds at 15 mA and 250 V to remove the AlO_x cap from the nanowire before depositing the leads. After a standard liftoff process in acetone, we deposited approximately 10 nm of HfO_x in an atomic layer deposition system at 120°C. This was followed by a fourth round of EBL for writing top gates. 10nm Ti/150 nm Au was deposited without Ar ion milling for the gates. Prior to each EBL step above, the chip was spin-coated with e-beam resist 950 PMMA A4 and vacuum baked overnight. Vacuum baking was used to avoid potential dewetting of the cold-deposited Sn at high temperatures. For developing the resist, we use 1:3 MIBK:IPA solution for 1 minute followed by rinsing in IPA for 1 minute, then blow drying the chip with nitrogen.

We have explored two different methods for extracting the $I_{sw}R_{n}$ product for SNS junctions - the threshold method and the peak finder method. In the threshold method, $I_{sw}$ is defined as the first current bias value where the differential resistance is non-zero, signaling a transition to the resistive state. In the peak finder method, $I_{sw}$ is equal to the current bias value at which the first peak in differential resistance occurs. The threshold method typically gives a switching current which is lower than that obtained from the peak finder method; this in turn leads to lower $I_{sw}R_{n}$ product using the threshold method. This is illustrated in Fig S2.

For devices where the switching current is small (less than 100 nA in our case), the high current bias plots (current bias up to a few $\mu A$) used for extracting $I_{sw}$ and $R_{n}$ do not resolve the switching current and can lead to incorrect estimation of the switching current using the peak finder method. Peak extraction is also a problem at negative gate voltages where the supercurrent magnitude is suppressed. Also, spurious dips or peaks in Rn due to charge jumps may cause an unexpected increase or decrease in $I_{sw}R_{n}$ values.

We also fabricated and measured one NS device in this study. The normal metal lead was formed by entirely covering Sn on one side of the junction with Ti/Au. Fig S5(a) shows an SEM image of the measured device. A top gate was fabricated at the boundary between the bare semiconductor and the semi-super segment to modulate the tunnel coupling between them. We performed pseudo 4-terminal $V_{bias}$ measurements for studying the superconducting gap and the magnetic field dependence. In Fig S5(b), we show the differential conductance as a function of the applied source drain bias and the top gate voltage. For this device, we obtain a superconducting gap $\Delta\approx$ $560\mu V$, comparable to the bulk gap of Sn. This value is also in good agreement with the gap value obtained from the SNS junctions measured. In Fig S5(c), we look at the differential conductance as a function of $V_{bias}$ and the magnetic field parallel to the nanowire. We see that the gap remains open till 1.5 T. In Fig S5(d), (e) and (f), we show $V_{bias}$ vs $V_{g}$ plots at different magnetic fields, with the gap softening at higher magnetic fields.