SliT: A strip-sensor readout chip
with subnanosecond time walk
for the J-PARC muon $g-2$/EDM experiment

The readout ASIC was implemented in the Silterra 180 nm CMOS technology. Table I summarizes the technological parameters. The front-end ASICs for silicon-strip sensors are requested to tolerate a high hit rate up to 1.4 MHz per strip with a stability to dynamically changing hit rates by a factor of 150 from the beginning to the end of measurements. In order to minimize the pileups, a pulse width for a typical minimum-ionizing particle (MIP) signal has to be smaller than 100 ns. Here, the pulse width is defined from a 1 MIP output, which intersects a threshold set at 0.3 MIP. For the further reduction of the pileups and precise detection of circular positron tracks from the muon decays, a subnanosecond time walk is of critical importance in analog processing blocks of the readout ASIC. The experimental requirements translated to concrete circuit specifications are summarized in Table II.

AC-coupled single-sided p-on-n type silicon-strip sensors with a double-metal structure were made by Hamamatsu Photonics K.K. [6]. The sensor thickness is 320 $\upmu$m. In this paper, the most probable value of the MIP charge is defined as 3.84 fC, which corresponds to an input charge of about 24,000 $e^{-}$. The sensor capacitance is approximately 17 pF, and the total detector capacitance $C_{\rm det}$ seen from an input of the ASIC is estimated to be less than 30 pF. This value includes the parasitic capacitance coming from Flexible Printed Circuits (FPCs) [7], which connect strip sensors with ASICs. Since the maximum wiring length inside the FPCs is about 250 mm, the parasitic capacitance from the FPCs is not negligible. The equivalent noise charge (ENC) of less than 1600 e^- at $C_{\rm det}=30$ pF is required.

In the previous studies, we started from a small-scale analog prototype in Silterra 180 nm CMOS technology. Then we fabricated module-prototype chips named “SliT128A” [8] and “SliT128B” [9]. The module-prototype ASICs included 128 readout channels, buffer memories, and other digital processing circuits to store and cope with timing information from the strip sensors. Since the time walk performance was measured as $\sim$17.2 ns in SliT128A, we introduced an additional CR block after the semi-Gaussian band-pass filter in SliT128B (see the next section for detailed description of this measure). As a result, the time walk improved to $\sim$2 ns, however, it was still larger than the requirement. A new readout chip named “SliT128C” improves the overall analog performance, e.g., the ENC, time walk, and jitter, by optimizing transistor parameters of bias circuits in SliT128B.

Fig. 2 shows the photograph of SliT128C. Inputs of 128 channels are aligned in staggered pads with a pitch of 100 $\upmu$m. The incident signals are processed from the left analog block to the right digital block. Power supply is provided from the top and bottom pads only, and digital outputs are accessed on the right-hand side. To suppress the digital cross talks, the analog and digital blocks are enclosed in distinct deep N-well islands.

Fig. 3 shows the signal processing chain of each channel. The strip sensor is AC-coupled to an input of the charge-sensitive amplifier (CSA), while test pulses can be injected via an AC-coupling capacitor of 100 fF. The CSA is based on a folded cascade configuration with a p-channel input transistor ($W/L=8~{}\upmu$m$/180$ nm). In terms of noise performance, we increased the folding number of the input transistor to $M~{}=~{}250$, which are placed in parallel. The feedback capacitor $C_{\rm f}$ was implemented by a metal-insulator-metal structure with a value of 170 fF. A transfer gate type FET was employed for the CSA DC-feedback component.

The CSA output is fed into a CR-RC shaping amplifier composed of a pole-zero cancellation circuit (PZC) and a second-order integration low-pass filter. The capacitors and resistance values in the PZC were selected to meet the equation of $C_{\rm f}\cdot R_{\rm f}=C_{\rm pz}\cdot R_{\rm pz}$. In the semi-Gaussian shaper, high-resistance p+ poly-silicons were chosen as resistors. Strictly speaking, the parameters of $C_{\rm sh1/sh2}$ and $R_{\rm sh1/sh2}$ have to meet the equation of $C_{\rm sh1}\cdot R_{\rm sh1}=4C_{\rm sh2}\cdot R_{\rm sh2}$ for the ideal case that the network functions as the second-order CR-RC shaper [10], however, we have tuned the actual values to minimize time walks by a SPICE simulation.

The shaper output is amplified by an inverting amplifier by a factor of two. This function is selectable with a CMOS switch on the outside chance that voltage slopes of the shaper output affect timing accuracy. After the inverting amplifier, the output is fed into two signal paths, one of which is buffered and connected to a discriminator. Baseline tuning is required to adjust the thresholds that is performed by two sets of 7-bit current DACs and resistors. The other signal path is connected to the additional CR circuit, which functions as a voltage differentiator.

In the previous chip, SliT128A, the hit timing was produced from the first-order CR-RC shaper with a peaking time of 50 ns and a single discriminator. This method, however, was not able to reduce the time walk of the discriminator rising edge below the requirement of 1 ns, even after the fine tuning of the threshold. By implementing the differentiator after the CR-RC shaper, we improved the time walks between 0.5 and 3 MIP signals. By differentiating the semi-Gaussian shape, the output shape becomes bipolar, which traverses the baseline given by $V_{\rm base}$ in Fig. 3. The traversing timing becomes independent of input charges. This method corresponds to the so-called “zero-crossing” architecture and the traversing timing locates at a peaking time of the preceding CR-RC filter. As a result, the discriminator rising edge from the differentiator path remains less than $100$ ns, and at the same time, the time walk can be considerably improved.

The noise level after the voltage differentiator becomes worse than the ENC of the CR-RC shaper. To suppress triggers on noise, we preserved the CR-RC shaper path and used both information to define the final pulses by making an AND operation. The leading-edge timing of the final output is determined from the differentiator, while the trailing-edge timing is determined from the CR-RC shaper. Precisely speaking, the noise bandwidths of the CR-RC and CR-RC-CR are theoretically the same, i.e., the differentiator introduces a low-frequency cutoff, whereas the upper cutoff frequency remains about the same [11]. The noise level is related with the reduction in peak amplitude of the bipolar shapes. This degraded slope also produces larger time jitter (not the time walk itself), compared with the CR-RC filter. The time jitter or temperature effect on the time walk is, however, averaged due to large event statistics and not a severe problem in our experiment. The time walk and time jitter estimated by the Monte Carlo simulation, including the device mismatch and parasitic effect, are listed in Table II.

The monitor lines were also implemented to examine analog waveforms at each processing point, e.g., the CSA, CR-RC shaper, differentiator etc. The 20-bit control registers are implemented to enable switches, i.e., a test pulse injection, the inverting amplifier, distinct discriminators, monitor lines, and tuning DACs for each channel.

Fig. 4 (a) shows the block diagram of the digital part. It consists of a signal interface (I/F), a memory controller, a serializer, a timing generator, and a parameter controller. The timing generator block provides the “Write Start” and “Read Start” signals to the memory controller, which are synchronized with an external 200 MHz clock. The parameter controller block is a slow control circuit for the registers of both the analog and digital parts. The signal interface block receives the discriminator outputs from the analog part. D-type flip-flops sample these signals by the external 200 MHz clock. After the first flip-flops, subsequent two D-type flip-flops resample these signals by 100 MHz clocks which are 180 degrees out of phase. This is because the sampling frequency of 200 MHz is close to the maximum clock frequency of logic circuits in the Silterra technology.

Fig. 4(b) shows the block diagram of the memory controller. The memory controller block receives two kinds of data, which are synchronized by different 100 MHz clocks, from the signal I/F block. When the memory-write controller block receives the “Write Start” signal, it starts to store data in SRAMs. The memories have 8192 word depths for each channel, and the data can be stored within 40.96 $\upmu$s ($=8192\times 5$ ns). The storing process continues until the SRAMs are full. When the memory-read controller block receives the “Read Start” signal, it reads out all of the data from memories and sends them to the serializer block. The data is then sent out by the LVDS drivers with a 50 MHz clock. The data are synchronized by the same 50 MHz clock in the backend electronics, e.g., an FPGA board in our applications, with the DDR (Double Data Rate) mode.

The performance of the SliT128C was evaluated with a test pulse from a function generator. A dedicated printed circuit board (PCB) was designed for performance testing. Fig. 5 shows the experimental setup. A bare die is directly mounted on the PCB and a light-shielding box is placed on the chip. The PCB is electrically connected to the ASIC by 25 $\upmu$m-diameter aluminum wires, and also connected with a commercial field programmable gate array (FPGA) board. We chose the Digilent Nexys Video [12] as an interface with a computer, which is a commercial rigid PCB with a Xilinx Artix-7 FPGA (XC7A200T). This FPGA board provides an easy-to-use programming environment and allows easy modifications to test logics. To store all data from SliT128C, a FIFO is programmed in the FPGA. The stored data are transferred to a computer via an Ethernet cable with the SiTCP protocol [13]. We evaluated the analog performance of 32 out of 128 readout channels, each of which was equipped with 33 pF as a pseudo-strip-sensor capacitance for the test.

The response of the monitor outputs was investigated to evaluate the analog waveform and dynamic range. Fig. 6 shows typical analog output signals, when a test pulse with 1 MIP charge was injected. The outputs of discriminators are superimposed in black. All monitor lines are functioning as designed. The peaking time and pulse width were 64.2 ns and 99.2 ns, respectively. Comparing with the values from a SPICE simulation (35.1 ns and 75 ns) as shown in Table II, we observe larger values due to a finite output-buffer performance to drive a large capacitive load of the bonding wire, $\sim$5 cm microstrips on the PCB, and the probe capacitance of $\sim$3.9 pF. The actual pulse width at the discriminator must be shorter than the monitor values, and can be estimated only from the discriminator pulse width described in the following section.

Fig. 7 shows a pulse height of the CR-RC output as a function of injected charges. The wide dynamic range is needed to avoid the saturation for the high hit-rate environment. The integrated non-linearity (INL) was measured as less than 1% and 3.8% in the ranges from 1.92 fC to 20 fC and from 1.92 fC to 30 fC, respectively. An INL of 5% is sufficient for our application. The corresponding dynamic range is larger than 7.8 MIP. We also confirmed that the channel-to-channel variation of offset voltages is within the amplitude of a 1.5 MIP charge that is reasonable to be compensated by 7-bit DACs.

The noise performance was evaluated by scanning the threshold with different injected charges (s-curve scan). First, we enabled only the discriminator in the CR-RC filter, and performed the threshold scans. Fig. 8 shows a counting efficiency as a function of the threshold DAC, a so-called s-curve for a typical channel. The counting efficiency was calculated from the digital outputs. By fitting a complementary error function, i.e., integrated Gaussian function, to the data, the center value and the standard deviation of the Gaussian function are obtained. The center value corresponds to the pulse height. The standard deviation indicates the noise level. One least significant bit (LSB) step size of the threshold DAC for the CR-RC shaper is equivalent to the input charge of 0.043 fC. We repeated this measurement for 32 readout channels, and plot the ENC distribution in Fig. 9. The average equivalent noise charge is measured to be $1547\pm 75$ electrons at $C_{\rm det}=33$ pF, where the uncertainty indicates the channel-to-channel variation. If we assume the simulated ENC dependence on the detector capacitance  (31 electrons/pF), we obtain the ENC to be 1454 electrons at $C_{\rm det}=30$ pF, which satisfies the requirement for the noise performance. The simulated ENC is $1210$ electrons at $C_{\rm det}=30$ pF. The ENC difference between the measurement and the simulation can arise due to various factors: parasitic input capacitance, digital crosstalk, and noise injection from the power supplies.

Based on the above results, we set the threshold voltage of the CR-RC shaper to match 1.53 fC which corresponds to an 0.3 MIP charge level in each channel. Then the threshold voltage for the voltage differentiator was adjusted to minimize the time walk. Fig. 10 shows the hit timing vs. threshold voltages of the voltage differentiator in a typical readout channel. The hit timing is defined as the leading-edge timing of the final output, which is determined by the differentiator. A plateau appeared in the hit timing by giving a proper threshold voltage to the differentiator. The time walk of our application is defined as a maximum timing variation in the range from 0.5 MIP to 3.0 MIP.  Fig. 11 shows the time walk distribution for the 32 readout channels. This result satisfies the requirement for the time walk and the mean value of the time walk was $0.38\pm 0.16$ ns, where the uncertainty indicates the channel-to-channel variation. We note that the hit timing over the injected charges of 3 MIP is increasing, however, we confirmed the plateau can be expanded up to 5 MIP by further tuning the bias of the shaping amplifiers.

The time over threshold (ToT) as a function of injected charge is shown in Fig. 12(a). The reconstruction quality of the positron tracks can be improved by filtering events based on the ToT information. As described in section II, the leading edge of the hit signal is determined either from the voltage differentiator or the single CR-RC shaper by the register setting. We compared the performance at the normal operating conditions, i.e., using outputs from both CR-RC and voltage differentiator in discriminators, in the case that the CR-RC path only is used to get the ToT values. Both cases are labeled as CRRC&DIFF (red) and CRRC (blue) in the figure. Averaged ToT of 32 channels at 1 MIP are determined as $34.1\pm 0.6$ ns (CRRC&DIFF) and $74.5\pm 1.6$ ns (CRRC).

We note that the ToT value at 1 MIP of the CRRC case (74.5 ns) can be compared with the simulation value of the pulse width (75 ns) as shown in Table II. The measurement results are close to the designed performance. The ToT of the CRRC&DIFF becomes flat above 15 fC. The non-saturation region can be expanded up to 20 fC by tuning the bias of the shaping amplifiers.

Fig. 12(b) shows the timing jitter ($\sigma$) as a function of the injected charge. The timing jitter becomes worse for smaller signals, since the leading edge of the hit signal is directly affected by the electrical noise. The average timing jitter at 1 MIP for 32 channels is $2.9\pm 0.1$ ns for the CRRC& DIFF case and $2.5\pm 0.1$ ns for the CRRC case. The jitters at 0.5 MIP is $4.8\pm 0.2$ ns for the CRRC & DIFF, and $4.5\pm 0.2$ ns for the CRRC. They are comparable with the sampling interval of 5 ns.

When the number of fired channels are increased, the instantaneous IR drop becomes a main issue to degrade the timing performance. This issue is related with the implementation of decoupling capacitors between supply powers and ground. In our application, the fired channels are estimated to be a few dozen channels at most, and thus, the performance degradation can be negligible in our application.

We supplied 1.8 V for an analog circuit and 1.8 V for a digital one. An additional dedicated bias voltage of 1.1 V is applied to the input transistors in the CSA for noise optimization and avoiding IR-drops. By measuring the current at each power line, power consumption was determined to be 0.13 W, 0.11 W, and 0.06 W for the analog, the digital, and the CSA, respectively. The total power consumption is 0.30 W per chip.