Scalable Nanophotonic-Electronic Spiking Neural Networks
Abstract
Spiking neural networks (SNN) provide a new computational paradigm capable of highly parallelized, real-time processing. Photonic devices are ideal for the design of high-bandwidth, parallel architectures matching the SNN computational paradigm. Co-integration of CMOS and photonic elements allow low-loss photonic devices to be combined with analog electronics for greater flexibility of nonlinear computational elements. As such, we designed and simulated an optoelectronic spiking neuron circuit on a monolithic silicon photonics (SiPh) process that replicates useful spiking behaviors beyond the leaky integrate-and-fire (LIF). Additionally, we explored two learning algorithms with the potential for on-chip learning using Mach-Zehnder Interferometric (MZI) meshes as synaptic interconnects. A variation of Random Backpropagation (RPB) was experimentally demonstrated on-chip and matched the performance of a standard linear regression on a simple classification task. Meanwhile, the Contrastive Hebbian Learning (CHL) rule was applied to a simulated neural network composed of MZI meshes for a random input-output mapping task. The CHL-trained MZI network performed better than random guessing but does not match the performance of the ideal neural network (without the constraints imposed by the MZI meshes). Through these efforts, we demonstrate that co-integrated CMOS and SiPh technologies are well-suited to the design of scalable SNN computing architectures.
Index Terms:
neuromorphic computing, spiking neural networks, nanophotonics, photonic integrated circuits, silicon photonics.I Introduction
Computation using spiking neural networks (SNN) yields three major architectural advantages: (1) the sparsity of communication between elements which reduces energy cost, (2) the binarization of communication without discretization of messages (i.e. all-or-nothing spike responses), and (3) completely asynchronous operation of computational units. At the architectural level, the spiking paradigm requires several computational elements in common to the traditional artificial neural network (ANN)—weighted addition, nonlinearity, and learning algorithms—though with the additional complexity of computation spread through time. Traditional computational approaches based on the von Neumann computing architecture—including modern system architectures equipped with graphical processing units (GPUs)—are not well-suited for the use of this computational paradigm due to the fundamental separation between computing and memory units and resulting serialization of many processing tasks. In turn, the traditional computing paradigm cannot efficiently support the requisite computational elements without significant simplification or long latencies thus warranting the development of new computer architectures. Neuromorphic design operates under the general principle that evolution has already produced a successful SNN architecture for operating under real-time, low-power conditions. Approaches to replicating this design employ a variety of digital, analog, or mixed-signal circuits that can be based on electronic, photonic, or optoelectronic devices. Nonetheless, substantially more work is necessary to determine the optimal approach to abstract, apply, and improve upon this evolutionary design.
Digital neuromorphic processors (such as TrueNorth[1], Loihi[2], SpiNNaker[3], etc.) increase the parallelization of processing by including a large number of cores that allow asynchronous computation—in contrast to GPU architectures—though this approach is not unlike a specialized and monolithic form of cluster computing. Though each core completes its operation in parallel, a desire for determinism in digital electronics necessitates synchronization between simulated time steps. This, in turn, limits full asynchronous operation which may prove to be prohibitive at biological network scales. On the other hand, analog electronic meshes can provide fully parallel computation, though the capacitance of electrical wire networks causes increases to both latency and power consumption.
Photonic and optical computing efforts have sought to exploit the nearly lossless and parallel communication capabilities of optical fibers into the domain of photonic integrated circuits (PICs). A number of demonstrations have already shown matrix multiplication and convolutional processing using non-spiking photonic circuits [4, 5, 6]. These devices use a combination of wavelength-division multiplexing (WDM) and space-division multiplexing (SDM) to manage multiply-and-accumulate (MAC) operations in parallel; thus, these schemes are also compatible with spike processing in synaptic networks. Choices of nonlinearity in spiking elements varies widely from one approach to another, though a major division can be made between all-optical and optoelectronic approaches. Optical nonlinearities typically have shorter lifetimes and can potentially service higher speed computation compared to electronic nonlinearities based on electronic charges or currents. However, the manipulation of these nonlinearities is governed mainly by material properties which are fixed after fabrication. Given that biological neural networks operate over a range of time-scales, it is preferable to have programmable elements in the neuron design. Optoelectronic approaches can take advantage of recent progress in the co-integration of CMOS circuitry with photonic devices to form flexible and programmable spiking neuromorphic computers.
In addition to the architectural benefits, SNNs offer provable advantages in solving graph algorithms, constraint satisfaction, and other optimization problems [7, 8, 9, 10]. Incorporating learning and training using Hebbian[11] and spike-timing-dependent plasticity (STDP)[12] algorithms also allows for the application of SNNs in many of the same contexts as deep neural networks (DNN). These learning rules have the additional architectural advantage of using only locally available information for the updating of each synapse. In principle, this means that all weight updates within the network can be calculated completely in parallel. With the appropriate network topology and training signals, Hebbian learning has also been shown capable of error-driven learning equivalent to backpropagation in deep and convolutional neural networks of moderate size [13, 14].
In this paper we will discuss the design of a nanophotonic-electronic neuromorphic architecture for native SNN computation with on-chip learning. Sec. II will provide a brief taxonomy of existing photonic and optoelectronic approaches to spiking neuron and optical matrix multiplication. Next, Sec. III will discuss the technologies and algorithms used, while addressing scalability and remaining design challenges. Finally, Sec. IV will detail future directions and perspectives for the design of photonic neuromorphic processors.
II Background and Survey
Spiking neural networks require two primary computational elements: (i) a nonlinear spiking unit that can integrate its inputs over time (the neuron) and (ii) a reconfigurable network to service weighted connections between these elements (the synaptic network). As previously alluded, the nonlinearities exploited for the design of spiking units can vary between all-optical and optoelectronic approaches, the choice of which can limit the choice of network elements to service communications between units.
II-A Spiking Nonlinearity
Excitability describes the ability of a system to quickly and temporarily deviate from its quiescent state following small perturbations and can be rigorously described through bifurcation analysis as done by Izhikevich [15]. Biological neurons are dynamical systems and have been classified into saddle-node and Andronov-Hopf bifurcations which correspond to integrator and resonator neurons respectively. Simply put, integrator neurons integrate their inputs and will generate a spike upon reaching some dynamic threshold, while a resonator neuron undergoes some internal subthreshold oscillation with an increased response and likelihood to generate a spike for inputs that fall at specific phases of a resonant frequency.
Computationally useful spiking neurons, however, need not be entirely biologically plausible. Instead, behavior is commonly summarized by the leaky-integrate-and-fire (LIF) neuron model. In the LIF model, the membrane potential constantly undergoes exponential decay towards its resting potential with discrete jumps at each input spike. When the membrane potential reaches a fixed threshold, the spike is generated and the potential is instantaneously returned to a reset potential. LIF neurons are only able to represent integrator neurons and lose much of the complexity of behaviors seen in biological neurons. Alternatively, Izhikevich devised a neuron model which faithfully reproduces a wide range of biologically observed behaviors using only four parameters and two coupled differential equations [16]. For a brief summary of computationally relevant neuron behaviors and a comparison of neuron models see [17]. Other taxonomies exist to classify neuron types according to these behaviors, though some evidence has shown that biological neurons may flexibly switch between these types based on the history of the cell [18]. As such, an ideal hardware implementation of spiking neurons would be capable of representing a range of neuron types for maximal computational ability.
A number of semiconductor lasers have been explored which create isomorphisms between the time dynamics of material parameters of active photonic elements and the cellular mechanisms of biological neurons. Researchers have exploited the time dynamics of photocarriers, thermal diffusion, optical modes, and polarization competition to create excitable laser devices with varying degrees of faithfulness to the biology. Photonic spiking neurons can be most meaningfully divided into two categories based on whether the device can accept optical or electrical inputs—some devices can be modulated by either, but electrical input may be preferred for the advantages in system design discussed in Sec. II-B.
Optical devices can be further classified into coherent and incoherent devices based on how incoming wavelengths are used to excite the active medium. In coherent excitable semiconductor lasers [19, 20, 21, 22, 23], the incoming signal interacts with a lasing cavity mode on the same wavelength to modulate the output signal directly. Excitability is induced by disturbing the balance between competing modes or polarizations which, with sufficient input energy, temporarily drive the extinction of one mode and amplification of the other. Bandwidth for such devices is bound by the cavity Q factor, with a time constant for energy dissipation given by . For incoherent devices [24, 25, 26, 27] the incoming signal interacts with some element within the cavity that indirectly modulates the output signal. This may take the form of optical pumping of the laser medium, or otherwise modulating the carrier populations which affect gain and saturation properties. Bandwidth for such approaches are limited by the dynamics of these carrier populations which are material dependent. Alternatively, optoelectronic approaches [28, 29] can allow for the design of analog circuitry with time-dynamics that can be fit to a variety of available neuron models, with lasers modulated by current injection in response to processed photodetector input. Optoelectronic designs are mainly limited by the total bandwidth of integrated photodetectors and electronics, though some estimates suggest that bandwidths upwards of 10 GHz can be expected; see [30] for a more in-depth review of various excitable semiconductor lasers with discussions of bifurcation paralleling Izhikevich’s analysis.
II-B Reconfigurable Networks
Given the ability of silicon waveguides to simultaneously support a wide range of wavelengths with negligible loss, on-chip optical networks are most efficiently parallelized using wavelength division multiplexing (WDM). Time-division multiplexing (TDM) offers another scheme for sharing computing resources over time, but the asynchronous and stochastic nature of SNNs is not likely to benefit from this technique. Using WDM, signals from each neuron can be routed according to wavelength and resources for matrix multiplication may potentially be used for multiple independent operations to support weight sharing and convolution. To support such architectures, different neurons must be distinguishable by output wavelength. However, the system does not need a unique wavelength for each neuron since most SNN architectures group neurons into layers that provide an additional level of hierarchy for routing structures.
Using a WDM approach, arrayed waveguide grating routers (AWGR) can be used to support all-to-all routing schemes between neural layers [31, 32, 33]. Inputs to each layer would be passed through reconfigurable optical matrix multipliers such as cross-bar networks, micro-ring resonator (MRR) banks, and mach-zehnder interferometry (MZI) meshes. MZI meshes can perform unitary matrix transformations that correspond to lossless multiplication and are thus particularly suitable for low-power neuromorphic computing. See [34] for a longer discussion on the design trade-offs between each of these devices. Sec. III-B describes our MZI mesh architecture, while Sec.III-C details algorithms for training SNNs using MZI meshes.
III Scalable Photonic SNN Technologies
III-A Towards Attojoule nanophotonic-electronic spiking neurons
Neurons provide nonlinearity and signal regeneration between each neural network layer. Our previous work [35] presents an optoelectronic neuron design with projected energy efficiency on the order of . Because the time-scales of electrical circuits are more tunable than photonic nonlinear materials, the neuron is more easily programmable while still taking advantage of low-loss communication provided by photonic interconnects. This design closely matches the behavioral characteristics of the Izhikevich neuron model to achieve a variety of neural behaviors. To move a step forward in realizing attojoule energy efficiencies, we have updated this design on a more advanced foundry platform.

Our previous foundry neuron design [35] also employs optoelectronics and a scalable MZI interconnect mesh, however, this design is not capable of the full range of neural behaviors described by the Izhikevich model. Using the GlobalFoundries (GF) 45SPCLO PDK, a new neuron was designed that can support a wider range of neural behaviors depending on applied voltage biasing. GF 45SPCLO is the successor of the GF 90WG PDK, and preserves the same CMOS-silicon photonic co-integration with a more advanced process node and additional metal routing layers. Fig. 1 shows the GF 45SPCLO neuron circuit design. The labeled red pins mark voltage biasing nodes that can be adjusted to achieve the desired neuron behavior. These nodes correspond to the control of an adjustable positive bias (), spiking threshold (), refractory feedback rate (), and adaptation rate (). The function of these node voltages is divided between membrane potential control and feedback potential control. Membrane potential controls adjust the spiking threshold and determine the current flow into membrane potential for each spike input. Feedback potential controls, , determine the strength of negative feedback on the membrane potential and the length of refractory period. Balanced photodetectors receive excitatory and inhibitory light input. The diode at the circuit output incorporates the I-V characteristics of the laser diode chosen for the design.
To demonstrate this design, we first simulate the basic spiking behavior in response to excitatory and inhibitory inputs simulated in Cadence Spectre (shown in Figure 2). The nodes of each measurement are matched to the color of each line in Figure 1. We include inhibitory inputs on spike #11 and #12 and can confirm from Fig. 2 that inhibitory input suppressed the membrane potential and output, which matches our expectation.

Next, we demonstrate three spiking patterns: regular spiking (RS), fast spiking (FS), and chattering (CH) in analogy to [16]. These behaviors can be achieved flexibly by modifying the voltages at each biasing pin, which allows a greater tolerance for mismatch between design and tapeout. These spiking patterns are shown in Figure 3, Figure 4, and Figure 5 respectively. Input photocurrents are simulated as step functions from to , node voltages corresponding to each behavior are set as follows:
1) Regular spiking: bias () low, threshold () low, refractory feedback () low, and frequency adaptation () low.
2) Fast spiking: bias () low, threshold () high, refractory feedback () low, and frequency adaptation () high.
3) Chattering: bias () medium, threshold () medium, refractory feedback () high, and frequency adaptation () high.
These simulations verify the ability of the neuron circuit to achieve various spiking patterns on the more advanced 45SPCLO process.



III-B Photonic MZI Mesh as Synaptic Network
The building block of an MZI Mesh is a 4-port device that consists of two 50:50 beam splitters and two-phase shifters, and as shown in Fig. 6 (b). The phase shifter , inside the interferometer, controls the power splitting ratio. Meanwhile, the phase shifter, , outside of the interferometer, controls the relative phase difference between the two coherent input ports. As demonstrated in Fig 6 (a), the tunable power splitting functionality is tested by sweeping applied DC voltage on the phase shifter . MZI Meshes can be arranged in several ways, with the most popular arrangements being the triangular[36] or rectangular[37] formations. Both of the formations can realize an arbitrary NN unitary matrix. There are a variety of applications where MZI Meshes are employed, such as mode-division multiplexing [38], free-space beamforming[39], quantum computing [40], and photonic neural networks [41]. Our work utilizes MZI Meshes as synaptic interconnections for bio-inspired neural networks and aims to integrate learning algorithms on the same chip. Although calibration procedures of the MZI Meshes are well-studied [42], training MZI Meshes as neural network (NN) interconnects remains challenging. Hughes et al. [43] proposed an in-situ training to realize the traditional backpropagation algorithm for MZI meshes, and recently Pai et al. [44] experimentally demonstrated the method. This in-situ training requires additional forward and backward light propagation with power monitoring for each phase shifter element at each step. There are various approaches to monitor power. For example, Pai et al. [44] utilized power tapping and grating couplers with an infrared camera to record the emitted power from MZI Meshes. Alternatively, Morichetti et al. [45] used a non-invasive power sensing device introduced for silicon waveguides. We exploited 1:99 power taps and Ge photodetectors (PDs) which are available as an instance in Process Design Kit (PDK) elements of the active silicon photonic multi-project-wafer (MPW) runs from the AIM Photonic foundry. Fig. 6 (a) shows photocurrent changes on the monitoring PDs with respect to applied voltage on phase-shifter . Although we used thermo-optics as a simple and practical phase-shifting mechanism, it is possible to utilize micro-electro-mechanical systems (MEMS) for even lower power consumption [46] in future designs.

Fig. 7 (b) shows the fabricated and tested 66 rectangular MZI Mesh with power taps after each 22 MZI unit as shown in Fig. 6 (b). At each output waveguide of the 66 mesh, a micro ring resonator (MRR) add-drop filter is placed with a PD on the drop ports, allowing for output monitoring by either optical or electrical means. When the MRR is at resonance, the output can be monitored and accessed through the electrical interface during the training. Alternatively, the MRR resonance wavelength can be tuned to let the optical signal propagate after the MZI Mesh. In this way, multiple MZI Mesh layers can be cascaded for DNN-like implementation. All the components are available in AIM Photonic’s PDK v4.0. The device is wirebonded on a fanout printed-circuit board. A USB interfaced multi-channel high current output digital to analog converter (DAC) unit drives the thermo-optic heaters and MRR add-drop filters. Similarly, the photocurrents are digitized by a USB interfaced multi-channel 250kSps analog-to-digital converter (ADC), as shown in Fig. 7 (a).

III-C Training and Inference
For the on-chip training demonstration, we targeted a linear classification problem with 4-dimensional input vectors and two output classes. We used the Iris flower dataset [47], consisting of 3 classes and 150 input samples. For simplicity in the proof-of-principle demonstration, we excluded one of the classes that is linearly separable from the other two classes. Therefore, a linear regression classifier can achieve a maximum of 94 true classifications over 100 samples. We use a single-mode cleaved fiber to couple a CW tunable laser source operating at to the chip. After the edge coupler, the first three 22 MZI stages act as tunable beam splitters and were used to generate coherent input vectors. First, the input generator phase-shifters are optimized adaptively to create desired 100 input samples. Next, optimum voltage values are recorded in a look-up table (LUT) to recall in the training and interference cycles.
One of the challenges of using MZI Meshes as a synaptic weight matrix is that controllable variables (phase shifters) do not explicitly map to individual weight matrix entries. In other words, adjusting a single phase shifter will affect multiple weight matrix entries. Clements et al. [37] devised a decomposition method for rectangular meshes. In machine learning, however, the optimum weight matrix is unknown at the beginning of training and the additional resources for continual adjustment and decomposition become intractable. Hughes et al. [43] demonstrated a method of differentiating the weight matrix w.r.t. each phase shifter. However, this method requires two optical propagation steps in addition to the initial inference step: one forward, and one backward. Therefore, an external controller is required to schedule each propagation, and light sources must be bidirectional. Moreover, during the additional optical propagation steps, power must be monitored for every phase shifter element. The number of phase shifters in the MZI mesh scales as for NN weight matrices, meaning () power monitoring is required. This presents remaining challenges for scalability in deep neural networks.
Here, we looked for more hardware-friendly solutions and, taking inspiration from biology, explored random backpropagation (RBP) and contrastive Hebbian learning (CHL) for MZI Meshes. In Section III-C1 we present an experimental demonstration of random backpropagation training for a linear classification task; Section III-C2 discusses the CHL algorithm and its relevance to human-like predictive error-driven learning.
III-C1 Random Backpropagation
In RBP, global error is backpropagated electrically from the end of the network. As such, RBP does not require optical backpropagation or power monitoring for each individual 22 MZI unit. An important difference between conventional BP and RBP is the direction of the gradient. BP follows the steepest gradient direction, which requires error to multiply the conjugate transpose of the forward weight matrix. In a digital computer, these forward weights are available in the memory unit, but for MZI Meshes, optical light would be physically backpropagated as discussed earlier. The original researchers demonstrated that a random backward weight matrix could also guarantee learning unless random backward weights are exactly orthogonal to the steepest backward weights [48]. Further, neuroscience studies observed that backward synaptic connections of neural networks in mammals are not fully symmetric [49, 50] giving biological credibility to the RBP algorithm. Direct feedback alignment, a variant of RBP, has also been demonstrated for MRR-based photonic weight matrices [51]. Given that tunable elements in the MRR bank have a one-to-one mapping with the synaptic weight matrix, it is computationally easier to calculate steepest gradient direction. Therefore, RBP can be more useful for MZI mesh training where this mapping is non-trivial. Nonetheless, MZI meshes are preferred for their ability to perform lossless matrix multiplication.
Appendix A summarizes our method of applying RBP on a SiPh MZI Mesh, while an illustration of our experimental setup is shown in Fig. 7 (a). The multiplication, addition, comparator, and memory buffer operations are realized in an external computer through Python scripts. Unlike conventional RBP, we draw a new random backward matrix for each iteration where the error is larger than the previous. With this modification, we empirically observed faster convergence to the classifier’s highest accuracy and the ability escape local minimums, as seen in the course search of Fig. 8 (a). Note, however, this additional operation may not be necessary for a network with a larger number of parameters and multiple synaptic layers. For example, in the papers [48, 49, 50, 51] the authors use fixed random backward weights. Future efforts will involve the real-time implementation of these operations by integrated electronic circuits within the mesh.

Fig. 8 (a) shows the interference accuracy of the SiPh MZI Mesh classifier for each epoch. In each epoch, 100 samples are forward propagated once. We use i.i.d. random backward weights uniformly distributed in the interval . During the coarse search cycle (), the classifier searches different local minimums, and after some epochs, the interference accuracy decreases due to large variance on random weights. We defined an accuracy limit (85 true labels among 100 samples) and switched to the fine search cycle () when the limit was reached. As seen in Fig. 8 (a), the coarse search cycle ended when the classifier labeled 89 samples correctly, and in the fine search cycle, 92 true labels were achieved. The confusion matrix for the ideal linear regression classifier and SiPh MZI Mesh classifier are presented in Fig. 8 (b). The SiPh MZI Mesh misclassified only two samples compared to the ordinary least squares linear regression model we built in the computer via scikit-learn Python package. We also implemented a numerical simulation for the MZI Meshes on the computer. From the simulation results, we observed that the SiPh MZI Meshes achieve the same accuracy as the linear regression model. Therefore, we concluded that reason for the misclassification of two input samples related to hardware imprecisions such as noise on the output PDs, electrical wires, thermal crosstalk between the phase shifters, etc.
Intuitively, traditional BP outperforms RBP in terms of convergence speed due to the steepest gradient direction. However, RBP is more hardware-friendly given that forward weights are unavailable and since phase shifter-to-weight mapping is not explicit in the MZI Meshes. Because the steepest direction for the gradient is not calculated, RBP does not require any power monitoring inside the MZI Meshes except for the input and output stages. Therefore, the PDs can scale with () for NN weight matrices. In the future, we plan to study RBP for larger SiPh MZI Meshes and more complex machine learning problems.
III-C2 Contrastive Hebbian Learning
In contrast to backpropagation where learning is based on credit towards global error, learning in biological systems is restricted to information local to a given synapse. Despite this, biological neural networks are able to autonomously develop expansive hierarchical abstractions of information useful for interpreting the environment. This represents a form of self-supervised learning that needs no explicit calculation of error, but instead relies on chemical signals marking recent spiking activity local to a synapse.
O’Reilly [13] proved that differences in activity at two distinct phases of network computation can drive a class of temporal-difference learning rules that is equivalent to backpropagation and gradient descent of errors. This equivalence, however, only holds for a multi-layer perceptron (MLP) with recurrent feedback connections between each layer as in Fig. 9 (a). The general learning rule has minor variations which have different properties, though an empirical test under common MLP tasks showed that the CHL variant often converges to a solution most quickly:
(1) |
where and are variables representing the activity of the th and th neuron, and dictates the rate of learning.
Superscripts denote the phase of activity that each variable represents. The minus phase of execution occurs first, and represents the network’s natural response to the given input sample. Next, in the plus phase, the target activity is imposed on the output layer and the network reaches a new equilibrium. For fastest implementation, the duration of each phase should be the minimum time required for stable output activity. Taking the product of activity of sending and receiving neurons roughly tracks their correlations during each phase. Taking the difference of this correlation in each phase forces the network to unlearn its natural response and learn the desired target activity. In a spiking network, activity in these phases can be represented by low pass filters of spike trains; however, non-spiking activity can be assumed to approximate a rate-coding of spiking activity that fits some non-linear activation function. Unlike backpropagation, however, the network architecture requires bidirectional synaptic connectivity (as shown between layer 1 and 2 of Fig. 9 (a)) such that information propagates in both directions. Because each neuron is asynchronous, recurrence does not increase computational complexity as it does on traditional computer architectures. Additionally, the locality of learning and agnosticism to the neuron nonlinearity is advantageous for spiking neuromorphic hardware.

Following the two-layer network structure depicted in Fig. 9 (a), we simulated an implementation of CHL on an ideal MZI-mesh neural network. A set of 40 input-output pairs were generated from randomly-distributed, uniform-magnitude, four-dimensional vectors. Each layer was simulated with four rate-coded neurons with a sigmoidal activation function; as such, each MZI mesh was simulated as a rectangular mesh. As in Fig. 6 (b), it is assumed that each MZI unit of each mesh contains four PDs for input and output monitoring. For simplicity, it is assumed that each neuron injects light to the mesh on a separate wavelength, and that the PD capacitance is large enough to reject the cross-term products between signals. Thus, the PD is assumed to linearly sum the power received from each wavelength. Because CHL assumes real-valued activation, phase shifter is neglected such that phase of each signal can be ignored. Following these assumptions, each MZI unit can be treated as a sub-network that applies the following transformation to signal amplitude at each arm:
(2) |
Given that CHL is agnostic to the neural nonlinearity, Eq. 1 can be directly applied to the photodetector outputs as long as they are measured correctly at the plus and minus phase. However, as seen in Eq. 2, the MZI mesh is not able to implement any arbitrary matrix. To resolve this, we can calculate derivatives that relate how a change in affects each individual weight. Next, we average the contribution from each to estimate the best overall change:
(3) |
Note, we use because it is simpler to calculate than . Assuming that the plus and minus activity of each detector is recorded locally, this rule can be applied to every MZI in each mesh all at once. Fig. 10 shows the root-mean-squared-error (RMSE) over each epoch for the aforementioned two-layer network, along with an ideal implementation (direct application of Eq. 1) and implementation with randomly selected . Learning is applied after each sample (not batched) with epochs of training and a learning rate, . Each implementation is initialized to the same starting matrices.

Our MZI implementation of CHL showed an decrease in RMSE over the course of training which is indicative of learning. However, the ideal implementation showed a significantly larger decrease of RMSE at . For comparison, the randomly varying network shows an increase of in RMSE, giving more credibility to the idea that the MZI-CHL implementation is capable of learning—albeit at a much slower rate than the ideal implementation. It is clear from the stochastic nature of RMSE in Fig 10 that this implementation is prone to local minimums and instability. Nonetheless, this simple simulation illustrates the ability of the CHL rule to train local synaptic weights without regard for the other connections in the synaptic mesh and provides proof of concept for its use in MZI meshes. Additionally, the MZI mesh is restricted to unitary matrices which preserve magnitude of the input vector (before neural nonlinearity). In contrast, the ideal implementation allows independent gain and attenuation of each weight in the synaptic network. More work is needed to determine strategies for mitigating these restrictions and characterizing learning with more bio-realistic neural nonlinearities.
III-C3 Predictive Error-Driven Learning
In the biology, however, target signals can only come from the network’s own activity in response to its observations; even in the case of instructed learning, a biological brain must interpret perceptual stimuli (i.e. auditory and visual) and transform them into intelligible target signals for training. More recent work by O’Reilly et al. [52] has shown that the human brain may generate its own target training signals through cortico-thalamo loops which constantly undergo phases of prediction and observation to reduce future errors in prediction. O’Reilly et al. postulate that the alpha cycle ( Hz) in the human brain demarcates iterations of such predictive error-driven learning, where plus and minus phases are separated by a bursting skip connection between primary processing regions and prediction-carrying regions (shown as the dotted connection in Fig. 9 (b)) that fire with a duty-cycle within the alpha rhythm; a simplified diagram of this neural network architecture can be seen in Fig. 9 (b). Over many iterations of such prediction and observation, abstract representations can be learned that are capable of transformation-invariant object-recognition[52]. The learning rule in this model is more complicated than CHL to include additional biologically relevant terms, though the error-driven learning is captured sufficiently by the simpler rule.
Bursting is important to enforce the 25% duty-cycle and thus generate activity differences between the plus and minus phases of the CHL rule. The skip connection between first-order processing and the prediction layers allows the representation of the latter to more accurately match the ground-truth observation in the plus phase. Thus, without an explicit target signal, the network learns to better predict future inputs. Because subsequent inputs are governed by causality and are constantly occurring, the network is also constantly learning to better understand its environment. This structure can even be repeated for higher-order processing layers to hierarchically form even deeper, more abstract predictions of the input space. Future work is needed to identify an optimal implementation of the CHL rule within the MZI mesh structure and subsequently employ this style of self-supervised learning.
IV Perspectives and Future Directions
IV-A Our Future System and Benchmarking
The nanophotonic-electronic spiking neuron is composed of three main components: a photodetector, a nonlinear electrical circuit, and a laser. The photodetector receives information from the synaptic network and converts the optical signal to an electrical signal. The electrical circuit is the core of the neuron and processes the inputs to generate output spike responses. The laser output regenerates signal power after each layer to supply synaptic fanout to subsequent layers. Our team will exploit attojoule photonics with quantum impedance conversion [53] and closely integrate with low-capacitance () electronics for monolithic integration on a silicon-on-insulator (SOI) platform. Using photonic communication between each SNN layer reduces capacitive charge associated with the interconnect wires [54] in comparable electronic circuits. Additionally, the photonic platform can allow neurons to communicate with other neurons at high speeds ( 10 GHz) independently of communication distance.
To calculate the projected energy consumption, we can examine the composition of each component in the attojoule nanophotonic-electronic spiking neuron design. The dynamic energy cost of the nonlinear electronic circuit and laser can be calculated by examining the transistor on-state currents and associated operation voltages and frequency. Meanwhile the parasitic energy cost can be calculated from the total capacitance and the leakage current. According to our previous work[35], the electrical circuit current flow inside the maximum spiking rate attojoule neuron is expected to be at voltage supply when the neuron is in the ON state, while the leakage current is in the OFF state. The expected nanolaser energy consumption is 4.4 fJ per spike for a fanout of 80 [54]. The parasitic capacitance includes the load capacitance on the photodetector, membrane capacitor, and transistor gate capacitance. According to the IRDS2020 [55] and [56], we expect the load capacitance of the photodetector to be around 0.1fF, and the simulated membrane capacitor to be 0.5fF. By considering closely integrated nanoelectronics at 10 fJ/bit energy efficiency and a fanout of 10-100 following the concept outlined by [54], the minimum dynamic input energy to generate a spike output is projected to be 200aJ/spike.
For input, the proposed attojoule neuron design will utilize a low-Q nanophotonic crystal photodector with a Ge/Si cavity. The photonic crystal creates a resonant cavity that increases the confinement of light and reduces the size of the absorption medium [57][58]. This allows for an ultra-low capacitance (0.1fF) nano-cavity PD that can generate sufficiently large voltage without amplification when combined with a high-impedance load [59]. In addition, minimizing the electrical wiring between PDs and the nonlinear electronic circuit also reduces power consumption [54]. Similarly for spiking output, a hybrid InAs/AlGaAs quantum-dot nanolaser with photonic crystal cavity can be employed.
Aside from neuron design, the scalability on interconnect is also a critical design challenge. MZI meshes show nearly lossless multiplication that is particularly suitable for large-scale low-power neuromorphic computing. However, the number of tunable elements, in an MZI mesh, grows polynomially with the number of neurons in the layer. As such, a control circuit must be designed that scales with a minimal additional computational complexity.
IV-B Footprint Efficiency
In the previous sections, we introduced and experimentally demonstrated bio-inspired on-chip training methods which improve the scalability of the SiPh MZI meshes for synaptic networks. We also simulated optoelectronic spiking neurons in GF 45SPCLO electronic-photonic hybrid platform and envisioned a scalable attojoule nanophotonic-electronic neuron design. However, one handicap of the proposed photonic neuromorphic system remains unaddressed, footprint efficiency. From our experience with commercial SiPh foundries, a 1616 MZI Meshes occupies a 12.5 chip area. Similarly, Lightmatter introduced their 6464 SiPh AI accelerator occupying a 150 chip area [60] which incorporates billions of transistors. We propose two solutions, Tensorized Photonic Neural Networks (TPNN) and 3D Electronic-Photonic Integrated Circuits (3D EPICs) to improve footprint efficiency and enable deep and wide photonic neuromorphic systems.
IV-B1 TPNN
There are three main methods to avoid over-parameterized neural networks and relieve hardware requirements such as weight pruning, quantization, and model compression [61]. Because photonic NNs are analog computers, available bit precision is already limited. Unlike electronics, a photonic system can easily offer all-to-all connectivity through wavelength and space-division multiplexing. Therefore, the benefits of weight pruning and quantization approaches are not significant. In contrast, model compression can result in fewer hardware resources and smaller footprints. We proposed and simulated an algorithm-hardware co-design approach: photonic tensorized neural networks [62]. Tensor-Train (TT) decomposition is a multi-dimensional array processing technique to represent large matrices in a low-rank approximation [63]. Although low-rank approximation may cause decreased performance in NNs, one could train NN models in TT-decomposed format so that performance degradation is minimized [64]. For some ML problems, low-rank approximation also serves as a regularization term and improves performance [65]. Moreover, in the simulations [66], we observed that TT-decomposed MZI meshes are more resilient to noise and hardware imprecision. Our simulations and benchmarks demonstrated that TPNN could improve the footprint-energy-efficiency product by orders of magnitude by using fewer 22 MZI units without decreasing accuracy below 95% in image classification tasks [67]. Future work will realize a SiPh end-to-end TPNN system and provide benchmarks for footprint-energy efficiency and performance.
IV-B2 3D EPIC
3D electronic ICs (EIC) promise low energy consumption, low noise, and high density because of shorter electrical wires [68]. The main enabling technology for 3D EICs is through-silicon vias (TSV). Although thermal relief and yield are the challenges, 3D integrated high bandwidth memories show clear advantages compared to 2D EICs. Similarly, 3D electronic-photonic ICs (EPICs) can achieve high density, low loss, and high bandwidth performance. Multi-layer silicon photonic devices are already available in commercial foundries. However, they rely on evanescent vertical couplers, which require relatively long taper lengths () and small layer distance () [69, 70]. As an alternative, our previous work demonstrates through silicon optical vias (TSOV) [71, 72] for 3D EPICS using 45degree reflectors and silicon vias[72]. Ultrafast laser inscription also allows for freeform shaping of waveguides useful for routing in three dimensions. This technique has already been demonstrated for orbital-angular momentum multiplexing/demultiplexing and optical beam steering applications[73]. 3D EPICs provide devices to be stacked vertically allowing for greater neuron density per area and thus the design of deeper and wider photonic neural networks.
IV-C Applications for SNNs
In relation to AI and machine learning, SNNs provide several advantages over modern computing paradigms for tasks which mimic the conditions in which they naturally evolved. Because SNNs process data over time in a continuous manner, they are well-suited to applications situated in real-time environments with single inference and learning instances presented at a time (such as event-based signal processing [74]). In addition, the spread of information over time allows multiple forms of memory at different time-scales similar to the human distinction between working [75], short-term [76], and long-term memories. Neuromorphic sensing and robotics are a common direction of applications of SNNs; for example, an adaptive robotic arm controller can provide reliable motor control as actuators wear down [77]. More speculatively, future devices might exploit these properties in the context of live audio and natural language processing for voice assistants, live-captioning services, or audio separation; similarly SNNs can be used for live video and lidar processing in autonomous vehicles or surveillance systems. SNNs are not ideal for batched computation—in which multiple training samples are computed in parallel and averaged for parallelism in training—however, data centers may still make use of the increased computational parallelism in tasks like the nearest-neighbor search which can be performs in constant time, , on neuromorphic chips like Loihi [78].
A major challenge of many modern DNN and reinforcement learning (RL) agents is the development of abstract, transformation-invariant representations of objects relevant to the task. In classification tasks, a neural network must transform its input space into a representation which most clearly separates each labeled class. Similarly, RL agents must be able to process their input space into a representation that best accentuates the value of potential actions. Predictive error-driven learning, modeled after the work of O’Reilly [52], has the potential to autonomously build deep hierarchies of abstraction for a given input space. For example, a learning agent could implicitly learn physical properties of the world such as gravity, buoyancy, and contact forces simply by observing its environment. In combination with complimentary learning systems for memory [79] and RL models based on the basal ganglia [80], a neuromorphic learning agent may be capable of replicating simple navigation and foraging behaviors which require the flexible application of knowledge and memory. Such a model could provide key insights for the development of self-motivated learning agents that exploit hierarchical representations to solve reinforced tasks. Developing dedicated spiking neuromorphic hardware and taking advantage of the energy-efficient and scalable photonic devices will allow the development of larger models and new computational paradigms. These developments can be applied in dynamic, noisy environments that are not well-handled by today’s machine learning efforts.
V Conclusion
We have discussed the advantages of dedicated SNN hardware and highlighted the benefits of nanophotonic-electronic design within this computational paradigm. Additionally, we argued that co-integration of photonic and electronic devices combines the high-bandwidth, low-power communication protocols of photonics with the well-established and flexible CMOS circuitry. Towards the construction of a photonic SNN computing architecture, we demonstrated an Izhikevich-inspired optoelectronic neuron design, implemented RPB on an MZI mesh, and simulated CHL on a rate-coded, MZI-mesh neural network. In addition, we proposed the construction of a powerful self-learning SNN computing architecture built from these technologies and based on predictive error-driven learning models of the human brain. Subsequently, we have discussed technologies for improving the scalability of neuron and network density through tensorization of large neural networks and 3D electronic-photonic integration. Finally, we discussed perspectives on the suitable applications of photonic SNNs and emphasized applications of interest for our own efforts.
Future work is needed to establish the optimal design for brain-inspired spiking networks. Modern ANNs have oversimplified neural nonlinearities due to the limitations of the von Neumann computing architecture. Meanwhile, the heterogeneity of neural behaviors in different regions of the human brain provide various methods of encoding information. As such, a deeper exploration of these encodings is warranted to fully leverage the computing power of SNNs. Furthermore, modern learning algorithms are designed for sequential processing that is not ideal for SNNs hardware. As such, considerable work is necessary to determine the most efficient on-chip implementation of local learning rules like CHL. Nonetheless, the design challenges are well worth the effort to provide alternative routes for continued advances in computation and signal processing in the face of slowing progress of transistor scaling. Our continued work will focus on the characterization and design of nanophotonic-electronic spiking neurons and their incorporation within scalable, MZI-based neural networks capable of on-chip local learning.
Acknowledgment
This work was funded in part by the Air Force Office of Scientific Research grant FA9550-181-1-0186.
This research is based upon work supported in part by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via [2021-21090200004]. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of ODNI, IARPA, or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for governmental purposes notwithstanding any copyright annotation therein.
The authors would like to thank GLOBALFOUNDRIES for providing silicon fabrication through the 90WG university program and for their technical assistance in 45SPCLO MPW runs.
Appendix A RBP Algorithm
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Yun-Jhu Lee received the B.S. in Life Science from the National Taiwan University, Taiwan. He is currently working towards the Ph.D degree in Electrical and Computer Engineering at the University of California, Davis. Research interests include neuromorphic computing, integrated photonics, MEMS, and control system. |
Mehmet Berkay On received the B.S. in Electrical and Electronics Engineering from the Bilkent University, Ankara, Turkey in 2018. He is currently working towards the Ph.D degree in Electrical and Computer Engineering at the University of California, Davis. Research interests are enerrgy-efficient photonic neuromorphic systems, RF-photonic signal processing, fiber-optic communication, and compressive sensing. |
Luis El Srouji received the B.S. in Applied Physics with an emphasis in Physical Electronics from the University of California, Davis in 2020. He is currently working towards the Ph.D degree in Electrical Engineering at the University of California, Davis. Research interests include the design of bio-physically accurate analog neuron circuits, development of learning algorithms for optoelectronic spiking neural networks, and fabrication of on-chip laser sources. |
Li Zhang Li Zhang received the B.S. degree in electronics and information technology and instrumentation from Zhejiang University, Hangzhou, China, in 2016. He is currently pursuing the Ph.D. degree in electrical engineering with the University of California at Davis, Davis, CA, USA. His research interests include ultra-wideband transceiver, trans-impedance amplifier and optical driver. |
S. J. Ben Yoo (Fellow, IEEE and Fellow, Optica) received the B.S. degree in electrical engineering with distinction, the M.S. degree in electrical engineering, and the Ph.D. degree in electrical engineering with a minor in physics, from Stanford University, Stanford, CA, USA, in 1984, 1986, and 1991, respectively. He is currently a Distinguished Professor of electrical engineering with UC Davis, Davis, CA, USA. His research with UC Davis includes 2D/3D photonic integration for fu- ture computing, communication, imaging, and navigation systems, micro/nano systems integration, and the future Internet. Prior to joining UC Davis in 1999, he was a Senior Research Scientist with Bellcore, leading technical efforts in integrated photonics, optical networking, and systems integration. His research activities with Bellcore included the next-generation internet, reconfigurable multiwavelength optical networks (MONET), wavelength interchanging cross connects, wavelength converters, vertical-cavity lasers, and high-speed modu- lators. He led the MONET testbed experimentation efforts, and participated in ATD/MONET systems integration and a number of standardization activities. Prior to joining Bellcore in 1991, he conducted research on nonlinear optical processes in quantum wells, a four-wave-mixing study of relaxation mechanisms in dye molecules, and ultrafast diffusion-driven photodetectors with Stanford University. He is a fellow of OSA, NIAC, and was the recipient of the DARPA Award for Sustained Excellence (1997), the Bellcore CEO Award (1998), the Mid-Career Research Faculty Award (2004 UC Davis), and the Senior Research Faculty Award (2011 UC Davis). |