RTL Subsetting: Extracting a Smaller RTL that Preserves a Subset of Functionality
Abstract.
Improving the scalability of formal verification and simulation of Register-Transfer-Level hardware design including hardware accelerators and processors is becoming an increasingly heated topic. Although various techniques such as abstraction, decomposition etc. have been applied to improve the scalibility, they are all aimed at general-purpose RTLs, i.e. they assume that the RTL’s functionality all needs to be verified or simulated and thus try to simply these tasks for the whole RTL. However, a neglected scenario is that only a subset of a RTL’s functionality (e.g. an instruction subset) will be used, which is common for accelerators with multiple functional modules. This means verification and simulation may be conducted only for a subset of the whole RTL, which becomes easier due to the reduced RTL size. This paper presents a brand-new technique to get a RTL subset that preserves a subset of functionalities of the whole RTL. More specifically, given an instruction subset that specifies the functionality subset, this technique enables us to find a RTL subset that suffices this instruction subset. In the paper, RTL subsetting is conducted on the module instance level of the RTL through an algorithm that determines which instances should be removed and finally outputs a RTL subset. Experiments on different sized accelerators and processors demonstrate that our technique has a satisfying performance even on large RTLs with over 50,000 registers.