Realization of all logic gates and memory latch in the SC-CNN cell of the simple nonlinear MLC circuit

Logic gates are building blocks of any digital circuit and computer architecture. In general, following Boolean algebra, the logic operations are performed by converting given two inputs into a single logical output. For any logic operation, both the inputs and outputs have two states, namely ’ON’ or ’TRUE’ and ’OFF’ or ’FALSE’ states Mano (2003). The reliability of logic operations depends on the reliable operations of systems chosen. Since the current demand for miniaturization of logic devices, speed of computation and low-power consumption devices, it is inevitable to design an appropriate system which is able to produce noise-immune gates. As a result, for the past two decades or more, several schemes are being proposed such as DNA/RNA computing Adleman (1994); Collier et al. (1999), quantum computing Ladd et al. (2010); Nielsen and Chuang (2002), nano computing Bachtold et al. (2001) and nonlinear dynamics based computing in order to replace or complement the existing computer architecture based on silicon chipsHopfield (1982); Sinha and Ditto (1998, 1999); Prusha and Lindner (1999); Murali et al. (2009a, b); Sinha et al. (2009); Guerra et al. (2010); Worschech et al. (2010); Zamora Munt and Masoller (2010); Zhang, Song, and He (2010); Bulsara et al. (2010); Singh and Sinha (2011); Dari et al. (2011a, b); Storni et al. (2012); Roychowdhury (2015); Kohar et al. (2017); Venkatesh, Venkatesan, and Lakshmanan (2017a, b); Neves, Voit, and Timme (2017); Kia, Lindner, and Ditto (2017); Murali et al. (2018); Manaoj Aravind, Murali, and Sinha (2018); Sathish Aravindh, Venkatesan, and Lakshmanan (2018); Sathish Aravindh et al. (2020). Among these methods, nonlinear dynamics based computing can make reliable and re-configurable computer architecture because the underlying nonlinear systems posses a large number of basic functions.

Utilizing the flexibility of nonlinear dynamical systems for storing, communicating and processing of information in computer architecture has been an active area of research in nonlinear dynamics. In this connection, Hopfield had constructed a memory device using artificial neural network to store and retrieve information Hopfield (1982). Sinha and Ditto proposed a chaos-computing scheme to emulate different logic elementsSinha and Ditto (1998, 1999). In an optimal window of noise, it was observed the possibility of occurrence of logic behavior and this phenomenon is termed as logical stochastic resonance(LSR)Murali et al. (2009a, b); Sinha et al. (2009); Bulsara et al. (2010). The present authors employed strange nonchaotic attractors to build dynamical logic gates Sathish Aravindh, Venkatesan, and Lakshmanan (2018); Sathish Aravindh et al. (2020); Sathish Aravindh, Venkatesan, and Lakshmanan (2020). Besides, self-sustained oscillators can function as latches and registers if Boolean logic states are associated with the phases of the oscillator signalsRoychowdhury (2015). Heteroclinic computing is another nonlinear phenomenon based computation using a collective system of nonlinear oscillators Ashwin and Borresen (2004, 2005).

Not only nonlinear dynamics based computing complements existing silicon based technology, there also exist several efforts to extend computation techniques to other domains such as opticalSingh and Sinha (2011), chemicalSinha et al. (2009); de Lacy Costello et al. (2009); Stevens et al. (2012), physicalSathish Aravindh, Venkatesan, and Lakshmanan (2018), mechanicalMahboob et al. (2011), biologicalGerstung, Timmer, and Fleck (2009); Ando et al. (2011), molecularCollier et al. (1999); Kompa and Levine (2001) and other areas of scienceMotoike et al. (2001); Sinha, Munakata, and Ditto (2002); Norrell and Socolar (2009); Zhang, Song, and He (2010); Mozeika, Saad, and Raymond (2010); Zhang et al. (2012); Miyamoto et al. (2010). Instead of needing multiple hardware for different types of computations, nonlinear dynamical systems can act as processors of a flexibly configured and reconfigured device to produce different logic gates Worschech et al. (2010). In practice, the generation of nonidealitic and ambient noise restricts the ability to obtain different logic gates in these systems Murali et al. (2009b). Thus it is essential to choose appropriate nonlinear-dynamics based computing systems to overcome these odds.

Further, most of the previous studies have focused to produce OR(NOR) and AND(NAND) logic gates Sinha and Ditto (1998, 1999); Prusha and Lindner (1999); Murali et al. (2009a, b); Kohar and Sinha (2012); Kohar, Murali, and Sinha (2014); Kohar et al. (2017); Venkatesh, Venkatesan, and Lakshmanan (2017a, b); Sathish Aravindh, Venkatesan, and Lakshmanan (2018); Sathish Aravindh et al. (2020). Obtaining Ex-OR (simply XOR) and Ex-NOR (XNOR) in dynamical systems are equally important since these gates are the basis of ubiquitous bit-by-bit addition Storni et al. (2012). A half adder consists of an XOR gate and AND gate. Other uses of XOR gate include subtractor, comparator and controlled inverter. XOR and XNOR gates are usually obtained by the concatenation of NOR and NAND gates.

In the literature, it has been shown that in several nonlinear-dynamics based concepts like chaos computing Ditto, Murali, and Sinha (2008), heteroclinic network for computation Ashwin and Borresen (2004, 2005); Bick and Rabinovich (2009); Schittler Neves and Timme (2012); Neves, Voit, and Timme (2017), etc. the richness of nonlinear dynamics can be exploited to obtain flexible and reconfigurable logic gates including XOR gates. In this connection, Sinha et al. have demonstrated the flexible parallel implementation of logic gates using chaotic elements Sinha, Munakata, and Ditto (2002). Peng et al. have explored piecewise-linear systems to construct all dynamical logic gates Peng et al. (2008, 2010). Campos-Canton et al. have reported electronics experiments to obtain NOR, NAND and XOR gates in a piece-wise linear system Campos-Cantón et al. (2010). In ref.Cafagna and Grassi (2006); Campos-Cantón et al. (2012a) the equation of the plane in analytical geometry has been used to build a contribution of SR flip-flop and basic logic gates Cafagna and Grassi (2006); Campos-Cantón et al. (2012a). Storni et al. have investigated LSR by extending the analysis to a three well potential to realize XOR logic gates Storni et al. (2012). In ref.Canton, Martienz, and Duron (2017), the authors have proposed a method and circuit for integrating a programmable matrix in the field of reconfigurable logic gates employing a nonlinear system and an efficient programmable rewiring Canton, Martienz, and Duron (2017). Also Campos-Canton et al. have reported a parameterized method to design multivibrator circuit via Chua’s circuit system Campos-Cantón et al. (2012b).

Further, Murali et al. have shown that if one applies two low amplitude square waves as inputs to a two-state system, the response of the system produces a logical output (NOR/OR) with a probability controlled by the interplay between noise and bistable dynamics of the system. That is the interplay of nonlinearity and noise produces a flexible and realizable logic behavior. The authors have termed this phenomenon as Logical Stochastic Resonance (LSR) Bulsara et al. (2010). For the past few years LSR has been realized in many nonlinear systems such as a nanoscale device Guerra et al. (2010), resonant tunnel diodes Worschech et al. (2010), a vertical cavity surface emitting laser Zamora Munt and Masoller (2010); Zhang, Song, and He (2010), a polarization bistable laser Singh and Sinha (2011), a chemical system Bulsara et al. (2010), synthetic gene networks Dari et al. (2011a), and so on. Recently, two of the present authors along with Venkatesh employed coupled dynamical systems to build dynamical logic gates by altering the value of the logic inputs Venkatesh, Venkatesan, and Lakshmanan (2017b, a).

Also Gupta et al. have examined the possibility of noise free LSR by driving a two-stable system with periodic forcing instead of random noise Gupta et al. (2011). Kohar et al. have found that periodic forcing enhances the LSR in noisy bistable systems with periodic forcing instead of random noise Kohar, Murali, and Sinha (2014). By replacing noise with high-frequency harmonics, Venkatesh et al. realized logic operations AND, OR and RS flip-flop in the MLC circuit and they termed this phenomenon as Logical Vibrational Resonance (LVR). LVR has been realized in a two-potential system Venkatesh and Venkatesan (2016); Venkatesh, Venkatesan, and Lakshmanan (2017b, a). Besides logic gates, LSR and LVR can be used to realize SR flip-flops Gui et al. (2020a, b); Vincent et al. (2021); Murali et al. (2021). Then the question arises whether LSR and LVR can produce all the logic gates including XOR gate when one employs a bistable system. One finds that practically this is not possible. The reason for this shortcoming is the bistable nonlinearity of the system. For this case all the logic gates are obtained by assuming that for the input state $(0,0)$, the response of the bistable system resides in the left well and for the input state $(1,1)$ it is in the right well and for the other input state $(0,1)/(1,0)$ it may be any one of the wells depending upon the logic operations chosen. With these assumptions, bistable nonlinear systems are well suited for producing OR/NOR and AND/NAND logic gates. However these assumptions are not sufficient enough to obtain the other logic gates, namely the XOR and XNOR gates. For example, an XOR gate admits a high logic output only if the inputs are at different logic levels [(0,1) or (1,0)] and low logic output only if the inputs are at the same logic level [(0,0) or (1,1)]. For this logic gate case, the assumption for obtaining logic gates in bistable nonlinear systems leads to a possible loss of information and further the bistable nonlinear systems are unable to hold the condition for XOR/XNOR logic gates. Thus, the bistable system is unable to produce XOR/XNOR gates. In this paper, we propose a solution by considering a three-well potential problem so as to implement all the logic elements including XOR gates.

It was also shown in several studies that the three well potential nonlinear systems which exhibit logical behaviors are better suited for computational purpose than the logical gates generated by the traditional bistable nonlinear systems when one considers aspects such as noise interference, waveform smoothness and bit error rate Lu et al. (2019); Liu and Liu (2014). Thus it is important to ask the question whether one can realize all the logic gates and memory latches in a single nonlinear circuit system. We address this issue in this paper.

We consider a State-Controlled Cellular Neural Network (SC-CNN) based Murali-Lakshmanan-Chua’s (MLC) circuit Günay (2010, 2010); Swathy and Thamilmaran (2014). This circuit is constructed by using two CNN cells and external forces including sinusoidal force, biasing and noise. The existing MLC consists of Chua’s diode and a linear resistor, a linear capacitor, and an inductor. The discrete inductor restricts the circuit for fabrications of ICs. Further, CNN is well suited when extending the analysis to the coupled system. Thus SC-CNN MLC is more advantageous than existing MLC in the aspects of hardware realization. We show that this nonautonomous oscillator when subjected to two aperiodic logical signals produces all the logic gates available in digital electronics. We also show that these logic gates are tolerant for an optimal range of noise intensity. Besides, it is reported that the fundamental logical behaviors such as OR/AND/XOR gates can be observed through one of the state variables of the circuit and for the realization of the complimentary logical operations NOR/NAND/XNOR gates the other state variable can be utilized. Further, we report the possibility of the occurrence of both high active SR flip-flop and low SR flip-flop as well because of the parallelism innate in this circuit. One can also further realize three-input gates in the circuit.

This paper is organized as follows. We discuss the dynamical mechanism for the implementation of logical gates in the three well potential system and present a basic study of the SC-CNN cell of the Murali-Lakshmanan-Chua’s (MLC) circuit in Sec.III and Sec.III, respectively. We present the experimental realization of CNN cell of the MLC circuit in Sec.IV. We also describe the experimental and numerical results for the realization of OR/NOR and AND/NAND gates, Exclusive-OR (XOR) and Exclusive-NOR (XNOR) logic gates, Set-Reset memory latch, effect of noise and three input gates in Sec.V. Finally, we conclude our analysis in Sec.VI.

Consider a general nonlinear system

Here $V(x)$ is a potential function of the nonlinear system. Assume that the potential $V(x)$ is three well. It has three potential wells and two potential barriers as shown in Fig.1. Here $E$, $I$, $\xi(t)$ and $fsin(\omega t)$ are the bias value, logical input value, Gaussian white noise with intensity ‘$D$’, and the amplitude of external periodic forcing, respectively. The system (1) is driven by two square wave signals, namely $I_{1}$ and $I_{2}$, which encode the logical inputs and the response of the system (1) is considered as the logical output. For example, the inputs $I_{1}$ and $I_{2}$ take the value $+\Delta$ for the binary logic number ‘1’ and for $-\Delta$ the binary logical value is ‘0’. Then, the four possible combinations viz. (0,0), (0,1)/(1,0) and (1,1) of the input streams $I_{1},I_{2}$ are merged into three distinct values $+2\Delta,0,-2\Delta$ as $I=I_{1}+I_{2}$. Thus, the resultant input signal $I$ is a three level aperiodic wave form. Depending on the logic input, the potential function of the system assumes three different forms. The output of logic gates is given by the well in which the state variable ‘x’ resides. More precisely, for OR gate if ‘x’ resides in the left well, we set the logic output as ‘0’, and ‘1’ if it resides in any of the center-well or right-well. In the XOR gate, the ON output is possible if one and only if one of the inputs to the gate is in the ON state. That is if both the inputs are ON states or both are OFF, an OFF output results. In this circumstance, a bistable system is not able to hold the three input states. Hence when we use a bistable nonlinear system for these kind of cases, it leads to an effective loss of information. To take care of this problem, we propose a solution by generalizing the chosen system from a bistable one to a three well potential system as described above. In particular we extend the scope of implementing the logic gates by increasing the numbers of potential wells in order to extend the possible input-output associations. For example, for the XOR gate we set the output to be logical ’1’ if the state value of the system lies between the two local maxima of the potential function, and it is assumed to be the logical value ’0’ otherwise. For the XNOR gate we set the output to be logical value ’0’ if the state of the system resides between the two local maxima of the potential function of the system and it is to be ’1’ if it resides anywhere in the other two potential wells. The truth table (see Table 1) for different input-output combinations is defined and summarized in Table.2.

Cellular Neural Network (CNN), introduced by Chua and Yang in 1988 Chua and Yang (1988), is a n-dimensional array of circuit elements of analog components such as OP-amps, resistors, and capacitors $(n=1,2,3...)$. It is constructed by a large number of intercoupled identical dynamical systems called cells. These cells or nodes are essentially modeled by nonlinear ordinary differential equations. CNN is a relatively simple structure and is easy to be implemented by appropriate electronic circuit. Thus it is a powerful tool for the emulation and implementation of nonlinear dynamical systems having complex dynamics. A generalization of the CNN paradigm in which the CNN cells locally share their outputs as well as their state variables with each other was introduced by Arena Arena et al. (1995). This generalization exploits an analog architecture of CNN known as State Controlled-CNN (SC-CNN). Many studies have been reported on designing and implementation of chaotic circuits in terms of SC-CNNs Günay (2010); Swathy and Thamilmaran (2014); Luo and Wang (2016). The advantages of a SC-CNN are that they are inductorless and are RC based circuitry only, thereby leading to the realization of hardware and VLSI implementations Manganaro, Arena, and Fortuna (2012). The other significant applications of these kind of CNNs are parallel computing and low-power consumption. With these motivating facts, in this paper we consider an SC-CNN frame work of the well known MLC circuit. This circuit is essentially perturbed by two aperiodic square waves and as a consequence we show that the resultant output exhibits parallel logic elements and memory latch. In order to discuss this framework further, we first consider the MLC circuit as shown in Fig.2.

The relationships between the various circuit variables and circuit parameters and the above dynamical variables and parameters can be obtained from Ref.Murali, Lakshmanan, and Chua (1994); Lakshmanan and Murali (1996); Lakshmanan and Rajasekar (2003). Earlier studies on the dimensionless version of the circuit when the parameters were fixed at $a=-1.02,\>b=-0.55,\>\gamma=0.015,\>\beta=1.0$ and $\omega=1.0$ were made. The quantity $f$ was varied in these studies Murali, Lakshmanan, and Chua (1994); Lakshmanan and Rajasekar (2003). The circuit exhibits various underlying dynamical features including period-doubling route to chaos, intermittent route, strange non-chaotic attractors (SNA), etc Lakshmanan and Murali (1996); Lakshmanan and Rajasekar (2003). Three of the present authors have also shown that when the quasiperiodically driven MLC circuit is subjected to two aperiodic and logical square waves, it reproduces logical response in both the SNAs and chaotic regimes of the circuit. The authors have shown that how these attractors are tolerant to noise, so that even one can emulate different logic functions Sathish Aravindh et al. (2020).

Following the work of Arena Arena et al. (1995), the SC-CNN associated with the MLC circuit can be generalized by the following dimensionless nonlinear state equations,

In Eq.(4), j is the cell index, $x_{j}$ and $y_{j}$ are the state variables and the cell outputs, respectively. Each $a_{j}$ represents a constant parameter and $i_{j}$ is the threshold value. Also in Eq.(4) $G_{0}$ and $G_{s}$ are linear combinations of the outputs and state variables, respectively, of the connected cells. A dynamic model of two generalized CNN cells corresponding to Eq.(4) can be defined as follows:

where $x_{1}$ and $x_{2}$ are state variables, and $y_{1}$ and $y_{2}$ are the corresponding outputs. The MLC circuit equation defined by Eq.(2) can be derived from Eq.(4), by assuming : $x=x_{1}$, $y=x_{2}$, $a_{1}=b-a$, $a_{12}=a_{21}=a_{2}=0$, $s_{11}=1-b$, $s_{12}=1$, $s_{21}=-\beta$, $s_{22}=1-\beta(1+\nu)$, $i_{1}=0$ and $i_{2}=F(t)$.

Consequently, from Eq.(4) the SC-CNN based MLC circuit model is organized as below :

Here $F(t)=E+\sqrt{D}\xi(t)+I+fsin(\omega t)$ and $I=I_{1}+I_{2}$, corresponding to two logic inputs, $E$ is the bias and the remaining parameters are fixed at $a=-1.02$, $b=-0.55$, $\nu=0.015$, $\beta=1.0$ and $\omega=1.0$. The MLC circuit in the framework of SC-CNN has been studied numerically, experimentally and analytically in ref.Günay (2010). The standard MLC circuit (Fig.2) consists of a nonlinear resistor which has the three-segment piece-wise characteristics of Chua’s diode, a linear resistor, a linear inductor, and a linear capacitor with sinusoidal voltage source. On the other hand the SC-CNN model of MLC circuit (see Fig.3) mainly consists of a few OP-AMPs along with RC based circuits. Thus the SC-CNN model of the MLC circuit is an inductor-less purely RC based circuit, which leads to the realization of hardware easily. In the present paper, we consider this circuit and investigate the effect of two aperiodic and logical square wave signals on the SC-CNN of MLC circuit.

Fig.3 represents the complete experimental setup for two SC-CNN cells which generate the dynamics of the SC-CNN based MLC circuit. It is clearly obvious from Fig.3, that the circuit consists of a CNN with two cells, corresponding to the dynamical variables $x_{1}\&x_{2}$ in Eq.(6). The two state variables $x_{1}$ and $x_{2}$ of Eq(6) are associated with the voltages across the two capacitors $C_{1}$ and $C_{2}$, respectively. The nonlinearity is simply implemented by taking into account the saturation of op-amps. The circuit realization of the SC-CNN based MLC circuit is achieved with the cell components: $R_{11}=207K\Omega,\>R_{12}=66K\Omega,\>R_{13}=100K\Omega,\>R_{14}=100K\Omega,\>R_{15}=1K\Omega,\>R_{16}=100K\Omega,\>R_{17}=100K\Omega,\>R_{N1}=220K\Omega,\>R_{N2}=3M\Omega,\>R_{N3}=180K\Omega,\>R_{N4}=16K\Omega,\>R_{21}=100K\Omega,\>R_{22}=6666.6K\Omega,\>R_{23}=100K\Omega,\>R_{24}=100K\Omega,\>R_{25}=1K\Omega,\>R_{26}=100K\Omega,\>R_{27}=100K\Omega,R_{31}-R_{38}=10K\Omega,~{}C_{1}=10nF,\>C_{2}=10nF,\>$ and active element $IC741$ type voltage op-amps with $\pm 12V$ supply voltages. All the experimental results are obtained by using Agilent (33220A) function generators and Agilent digital oscilloscope (DSO 7014B). The amplitude of the forcing signal $f$ is used to study the dynamics of the CNN based model.

We have investigated the effect of logic square wave signals on the SC-CNN of MLC circuit system. Exploiting the hopping of attractors generated by this circuit, we have found that the circuit can emulate all basic logic operations corresponding to the logic gates OR, AND, NOR, NAND, XOR and XNOR and memory latch element RS flip-flop. It is also shown that all these logic behaviors are tolerant to noise. We have extended the scope of obtaining the logic gates by even feeding higher order inputs, specifically three-inputs. Results obtained by numerical simulations are in good agreement with experimental demonstration. Our study throws some useful light in replacing the existing computer technology with a minimal hardware.

It is clearly evident from our studies that the SC-CNN model of the MLC circuit can function as logic gates as well as memory latch even for small-amplitudes of the input signal. As a result, it consumes only a small power. Further, the same circuit can be used to produce a logic output corresponding to three-input logic. Thus this circuit may be used as two-input and three-input logic gates as well. The low active RS flip-flop and the high active RS flip-flop are constructed by cross-coupling of two NAND gates and cross-coupling of two NOR gates. Hence, the same MLC circuit can produce low active RS flip-flop through one state variable and high active RS flip-flop through another state variable. Further, the circuit can potentially operate in noisy environments.
Thus, the circuit can function not only in a noisy atmosphere but can also be capable of utilizing its resources by configuring the circuit into two-input, as well as three input gates and also as a memory device depending on the requirement. For instance, if we need to run a program, the circuit will mimic as logic gates of two inputs or three inputs, and on the other hand, for processing of data, the circuit will mimic as memory device which enables one to utilize it optimally. Apart from the computer architecture, the circuit morphs into a memory latch which may lead to acting as an electronic switching-de bouncer.

In this paper, we have proved that the underlying chaotic trajectories, which hop in different quadrants of the phase-space, induce parallel logic operations and memory latch in the SC-CNN of the MLC circuit and this feature may be considered for the replacement of currently existing processors and also as a remedy for Moore’s lawKia, Lindner, and Ditto (2017). Further one has to study the important features of this circuit such as access clock time, access energies and cell feature size and compare them with the existing technology, provide technically feasibility of the circuit for design and development of dynamic architecture. We hope to pursue these aspects in the near feature.

All authors contributed equally.

P.A. and A.V. acknowledge the DST-SERB for providing financial support for a research project under Grant No.EMR/2017/002813. M.S. sincerely thanks the Council of Scientific & Industrial Research, India for providing a fellowship under SRF Scheme No.08/711(0001)2K19-EMR-I. A.V. also acknowledges the DST-FIST for supporting experimental work under Grant No.SR/FST/College-2018-372(C). M.L. acknowledges the DST-SERB Distinguished Fellowship program under Grant No.SB/DF/04/2017 for financial support.

The data that support the findings of this study are available from the corresponding author upon reasonable request.