Real-Time Adaptive Neural Network on FPGA: Enhancing Adaptability through Dynamic Classifier Selection

Neural networks[1], a branch of machine learning[2], lead current computational research. They excel by discerning intricate non-linear patterns in data. Mirroring the human brain’s neural structures, these systems are made up of interconnected nodes or neurons. These nodes cooperate in processing and conveying data. A system’s complexity, assessed by its hidden layers and number of neurons, directly impacts its effectiveness and versatility for diverse roles. Such networks find applications in various sectors like business[3], renewable energy[4], healthcare[5], and more[6], indicating their essential role in recent problem solving.

The effectiveness of neural networks is offset by their considerable computational demands, which escalate as structural intricacy grows. This has accelerated the quest for ideal computational platforms. Conventional systems, such as CPU-based architectures and GPUs, have provided foundational support. but there is a shift toward reconfigurable architectures[7, 8, 9]. Defined by their aptitude for post-fabrication alterations, these configurations deliver a synthesis of performance and adaptability. They facilitate hardware-level modifications, preserving the sort of flexibility usually linked with software environments.

Field-Programmable Gate Arrays (FPGAs) serve as prime representations of such reconfigurable systems. Their innate parallel processing capability, paired with immediate configuration options, designates them as a suitable neural network foundation . FPGAs promise tailored neural network frameworks[7], optimizing both operational speed and energy conservation[10].

In the advancing field of FPGA-based dynamic reconfigurable neural networks implementation, multiple pivotal research works have surfaced, each tackling specific issues and presenting novel solutions. the research [11] centered on the adaptation of Binary Neural Networks (BNNs) for FPGAs, particularly when faced with resource constraints. Examining their findings, a method grounded in mixed-integer linear programming became evident. This method, when melded with dynamic partial reconfiguration[12], facilitated a streamlined BNN implementation on a Zynq-7020 FPGA.

In parallel, another research [13] unveiled the dynamic reconfigurable CNN accelerator (EDRCA) structure, targeting the challenges posed by hardware limitations in embedded edge computing environments. By harnessing dynamic reconfiguration capabilities specific to FPGAs, the EDRCA adeptly navigated these challenges, introducing a methodology designed to enhance efficiency while minimizing resource utilization.

Finally, the work by [14] presented a novel design approach tailored for economical neural network functionalities on FPGA. Central to this approach were ”flexible” layers, crafted to fulfill dual functions, leading to a reduction in layer count. Evaluations conducted on an Altera Arria 10 FPGA indicated a noteworthy decrease in resource consumption, with these innovative layers maintaining precision and adaptability across varied applications.

In the current research, we investigate the role of dynamic classifier selection in enhancing classification accuracy within a hardware implementation context. Unlike previous studies, which primarily focus on partial reconfiguration tailored to specific tasks or applications, our approach leverages partial reconfiguration based on the unique characteristics of each data point. This method produces a system that is both highly adaptive and precisely tuned, effectively balancing accuracy with resource efficiency. Our findings advance the existing body of knowledge by presenting a novel data-driven strategy for improving system adaptability and optimization.

In the devised neural network architecture, the emphasis is on creating a parameterized architecture that allows for a variable number of neurons and hidden layers, This design is particularly tailored to accommodate hidden layers that utilize Multiply-Accumulate (MAC) computations and Rectified Linear Unit (ReLU) activations.

Our FPGA-based neural network architecture is designed for flexibility, allowing parametrized numbers of neurons and hidden layers. Each neuron in the hidden layers performs a Multiply-Accumulate (MAC) operation, followed by a Rectified Linear Unit (ReLU) activation function.

Within the FPGA-based layout, each neuron in the hidden layers is precisely designed for executing a MAC operation on its array of input values. the neuron multiplies each input element $\mathbf{X}$ with a corresponding weight $\mathbf{W}$ and subsequently adds a bias term $\mathbf{b}$, mathematically represented as

After the MAC operation, a Rectified Linear Unit (ReLU) activation function adds non-linearity to the neural model. In hardware, ReLU is implemented using a comparator and a 2:1 Multiplexer (MUX). The comparator evaluates the MAC output $\mathbf{s}$ and produces a binary control signal. This signal directs the MUX to output either the original MAC value or zero, effectively implementing the ReLU function:

In the final output layer, we use an argmax function instead of the typical softmax activation. This choice prioritizes classification accuracy over detailed class probability distributions. The argmax identifies the neuron with the highest output and converts it to a one-hot encoded vector. This approach reduces computational complexity, simplifies hardware implementation, and speeds up inference

Figure 4 illustrates the structure of various neural network models in our ensemble. Each constituent model differs based on two fundamental parameters: neuron count and layer count. This variance serves dual purposes. Primarily, it augments ensemble diversity, an essential element for the robustness of the Dynamic Classifier Selection mechanism deployed on FPGAs. Additionally, this diversity is strategically designed to amplify system accuracy, constituting a substantial advantage over reliance on a singular neural network configuration. Equipped with a diverse ensemble of neural network models, the adaptative neural network possesses the capability to dynamically allocate the most suitable model for individual test instances using partial reconfiguration.

The foundation of our architecture is constituted by the Processing System (PS) incorporated into the Zynq System on Chip (SoC). As delineated in Figure 5,the PS is crucial in managing the operations of individual neural network modules as well as the competence estimator. This management is made possible due to the inherent high-performance, adaptability, and energy-efficient characteristics of Zynq platforms. Data transfer between our neural networks and competence estimator occurs via the AXI Direct Memory Access (DMA) and AXI Interconnect systems. The AXI DMA plays a vital role in facilitating efficient data movement between system memory and neural network implementations. Furthermore, the AXI Interconnect operates using the AXI4-Lite protocol, which is instrumental in enabling the architecture to interpret output data result from both the accelerators and the competence estimator. One feature of our architectural design is the incorporation of a Reconfigurable Partition (RP) region. Neural networks implementations are situated within this RP area, interfacing with the FPGA through a Dynamic Function eXchange (DFX) decoupler. Control over the DFX decoupler is exerted by an GPIO.

Following an in-depth exploration of parameter tuning, specifically concerning the number of centroids for the competence estimator and the configurations of hidden layers in the neural network models, we now pivot to the results. This subsequent analysis leverages the optimized parameters to provide a quantitative assessment of the real-time adaptive neural network.

Figures 6, 7, and 8 illustrate a numerical comparison between a real-time adaptive neural network, based on a DCS architecture, and the individual neural network models that make up the ensemble. The data shows that, for the German Credit dataset, the DCS-based architecture achieved an accuracy rate of 84.66%, which is 8% higher than the most accurate individual model, which recorded 76.66%. Similarly, for the Diabetes dataset, the DCS-based architecture attained an accuracy of 87.06%, surpassing the leading individual model’s accuracy of 82.75%. Lastly, in the Vehicle Silhouette dataset, the DCS-based architecture achieved an accuracy of 94.48%, significantly outperforming the highest-scoring individual model, which had an accuracy of 88.97%.

In conclusion, this study provides a comprehensive evaluation of a real-time, adaptive neural network using a DCS-based structural framework, tested across three diverse datasets. By optimizing parameters, the architecture consistently outperformed individual ensemble models in classification accuracy. Resource usage was significantly reduced by up to 109.28% through partial reconfiguration compared to a static implementation. These findings confirm the high performance of the architecture and demonstrate its practical applicability in scenarios where balancing accuracy and resource efficiency is crucial.