Readout system and testbeam results of the RD50-MPW2 HV-CMOS pixel chip

Depleted monolithic active pixel sensors (DMAPS) are a promising option for future tracking detectors in high energy physics. The availability of high-resistivity Si substrates and High Voltage (HV) capable structures in commercial CMOS processing makes them suitable as detectors in high-luminosity environments. DMAP sensors integrate the sensing diode into the bulk silicon of commercial CMOS chips. It also allows to use very small transistors which results in high granularity pixels with sophisticated in-pixel logic. Thus, amplification, sampling and digitization of signals as well as timing measurement and data reduction can be done on-chip.

The RD50 HV-CMOS group is studying radiation-hard DMAP sensors in the course of the CERN RD50 collaboration. This includes not only sensor development itself, but also characterization, electronics for data acquisition (DAQ) and readout software. This contribution focuses on the DAQ system and data flow of the RD50-MPW2 chip.

The first chip developed by the RD50 HV-CMOS group was manufactured in a multi project wafer (MPW) run and called RD50-MPW1. The chip was fabricated in the LFoundry 150nm process with a wafer thickness of 280µm. Measurements have shown, that the analog behavior of RD50-MPW1 was suffering from high leakage current and low breakdown voltage [1]. Moreover the chip showed some shortcomings in the digital readout. In order to tackle one issue after the other, the group decided to focus on improvements of the analog behavior of the pixel cell and designed a second iteration of the chip, the RD50-MPW2. The chip only has an analog front end in the pixels and no digital readout. As a result of these improvements, the pixel in the active matrix have been enlarged from 50µm x 50µm in RD50-MPW1 to 60µm x 60µm in RD50-MPW2, still focusing on the minimal possible size to achieve a highly granular matrix. An enlarged distance between the collection electrode and the biasing implant lead to a decrease of leakage current by four orders of magnitude. This massive improvement is suitable to be used in future tracking devices, where power dissipation is one of the big challenges. The analog characteristics and performance have been presented for example in [2].

In the course of characterizing and testing of RD50-MPW1 and later the RD50-MPW2 chips, a readout chain to be used in laboratory measurements as well as for beam tests has been implemented. In addition to the standalone data acquisition, this readout system provides techniques to synchronize with other detectors by an AIDA trigger logic unit (TLU) [3].

RD50-MPW2 consist of different test structures for studying the analog behavior of the chip [4]. One main part is the active pixel matrix, which is depicted in figure 2. It includes a bias block, configuration registers (implemented as shift register) and the pixel matrix itself with 8 by 8 pixels and a size of 60µm x 60µm each. Each pixel has a charge sensitive amplifier (CSA), an analog output after a source follower, called SFOUT, and a digital output after a comparator, called COMPOUT, as shown in Figure 2. The matrix provides pixels of two different flavors of readout: columns 0-3 are continuous reset pixels, while columns 4-7 are switched reset pixels. They differ in their feedback loop of the CSA. The feedback capacitor of the continuous reset pixel is continuously discharged by a fixed current $\rm I_{FB\_CONT}$ source, leading to an amplitude dependent output signal length. For the switched reset pixel, the feedback capacitor is discharged by a comparably high current $\rm I_{FB\_SW}$ source, which is switched on as soon as the signal is above a threshold and COMPOUT is high, resulting in a charge independent pulse length. A pixel from the latter type is chosen for all measurements in this contribution.

It is important to mention that the matrix is analog only and moreover only one pixel at a time can be read out. The output of each pixel is tri-stated and ORed together for each column and all columns are again ORed together and routed to a bonding pad. This is done for both SFOUT and COMPOUT, respectively.

The DAQ system is based on the Caribou framework [5], which includes hardware, firmware and software packages for configuring, powering and reading out pixels sensors. A detailed description of the setup used for RD50-MPW2 can be found in [6]. This contribution focuses on firmware developments.

Figure 3 shows a schematic of the standalone firmware, which can be used for laboratory measurements such as charge injection by the integrated injection circuit and charge generation by a radioactive source. The COMPOUT is buffered and connected to the FPGA (located at the Xilinx SoC ZC706 Evaluation Board, which is part of Caribou). This simple implementation includes a counter with a 200MHz clock input which is set and reset at the two edges of the pulse. It provides the 16-bit time over threshold (ToT) value at the output. Furthermore, one edge is shaped and counted in an asynchronous counter, which provides another 16-bit as output for counting particles. Those two times 16 bits are feed into the AXI FIFO, which is part of the standard AXI-bus from Xilinx [7].

The functions to access these FIFOs with the CPU are already implemented in the Caribou framework. The readout software just polls the AXI FIFOs every 100µs and writes the values into an ASCII file. The integrated peary command-line interface (peary_cli) is used for this purpose.

In order to test the standalone firmware RD50-MPW2 serves as device under test (DUT) and is put directly into the beam. As one can see in figure 6, the ToT value is independent from deposited energy for switched reset pixels, since the CSA is resetting nearly instantaneous after the switch is closed. The standalone firmware of RD50-MPW2 roughly measures this value as well, but with a bin size of 5 ns, which is needed for measuring longer pulses from the other pixel flavour. Calibration to get charge in units of electrons has not been performed yet.

In order to test the testbeam-firmware, RD50-MPW2 is put in the middle of a beam telescope, which uses two double sided silicon strip detectors (DSSDs) upstream and two DSSDs downstream of the DUT. The telescope is triggered by the coincidence of two scintillators, which are located at the very back of the setup. Analysis of the tracking capability of RD50-MPW2 is ongoing. Due to small geometric acceptance (just one single pixel is recorded at the same time) very high statistics is needed to get reliable results for tracking studies. This is in contradiction to the maximum rate of the telescope of 30 kHz. Thus the goal of this setup is to measure pixel efficiency, which can be done with a single pixel.

In this paper we report the first data taking with the RD50-MPW2 DMAPS chip in a testbeam environment. It has been shown that both readout firmware versions work very well and demonstrate a good agreement of the analog performance of the chip with simulation results. Also the synchronization of the chip with other detectors is working and analysis of tracking data shows consistent results. The main goal of this measurement was to familiarize with the special high-rate, but low-energy environment at MedAustron and prepare the DAQ system and analysis software for the successor chip of RD50-MPW2, which has been achieved.

Currently, RD50-MPW3 is being developed which will have a digital front end and the capability of reading out the full matrix. Knowledge gained for RD50-MPW2 in DAQ and analysis will be a valuable input for the study of this successor sensor.

This work was performed in the framework of the CERN RD50 collaboration. This project has received funding from Austrian Research Promotion Agency (FFG), grant number 878691.