Performance Limit and Coding Schemes for Resistive Random-Access Memory Channels
Abstract
Resistive random-access memory (ReRAM) is a promising candidate for the next generation non-volatile memory technology due to its simple read/write operations and high storage density. However, its crossbar array structure causes a severe interference effect known as the “sneak path.” In this paper, we propose channel coding techniques that can mitigate both the sneak-path interference and the channel noise. The main challenge is that the sneak-path interference is data-dependent, and also correlated within a memory array, and hence the conventional error correction coding scheme will be inadequate. In this work, we propose an across-array coding strategy that assigns a codeword to multiple independent memory arrays, and exploit a real-time channel estimation scheme to estimate the instantaneous status of the ReRAM channel. Since the coded bits from different arrays experience independent channels, a “diversity” gain can be obtained during decoding, and when the codeword is adequately distributed over different memory arrays, the code actually performs as that over an uncorrelated channel. By performing decoding based on the scheme of treating-interference-as-noise (TIN), the ReRAM channel over different memory arrays is equivalent to a block varying channel we defined, for which we propose both the capacity bounds and a coding scheme. The proposed coding scheme consists of a serial concatenation of an optimized error correction code with a data shaper, which enables the ReRAM system to achieve a near capacity limit storage efficiency.
Index Terms:
ReRAM, sneak path, across-array coding, data shapingI Introduction
Resistive random-access memory (ReRAM) is an emerging non-volatile memory technology that changes the resistance value of a memristor to represent two states of the binary user data: the High-Resistance State corresponding to logic 0 while the Low-Resistance State corresponding to logic 1. The memristor cell is positioned on each row-column intersection of a crossbar structure, which offers a huge density advantage for ReRAM systems [1].
When a cell in a memory array is read, voltage is applied to the memristor cell, and the current flows through the memristor and senses the resistance value. If the memristor is detected with a High-Resistance State, the bit is decided to be a ‘0’; if it is detected with a Low-Resistance State, the bit is determined to be a ‘1’. A fundamental drawback of the ReRAM crossbar array is the sneak-path problem [2]. Sneak paths are undesirable paths in parallel to the selected cell for reading. The current goes through the sneak paths and degrades the measured resistance value. Sneak paths are detrimental when a cell with a High-Resistance State is read because the resistance degradation may lead to an erroneous decision.
In the literature, several works [3, 4, 5] tackled the sneak-path problem by using information and communication theoretical frameworks. In particular, Y. Cassuto et al. [3] studied the maximum storage efficiency when the constrained codes are employed to completely avoid sneak paths. This method incurs a high code rate loss, especially when the array size is large. Y. Cassuto et al. proved that as the array size approaches infinity, the storage information rate approaches 0 in order to achieve a sneak-path free channel. On the other hand, a commonly used method to eliminate the sneak paths is to introduce a cell selector in series to each array cell. However, these selectors are also prone to failure due to the imperfections of the memory fabrication and maintenance process, leading to the reoccurrence of the sneak paths [4][5]. Y. Ben-Hur [4] and Zehui et al. [5] considered ReRAM systems with imperfect selectors which fail with a certain probability. They built a probabilistic sneak-path model and developed the corresponding data detection schemes. A main challenge for the ReRAM channel is that the sneak-path induced interference to the channel is data-dependent. Moreover, the sneak-path interference is also correlated between different locations of the crossbar array. Previous work [4] developed single-cell data detection schemes that detect the data for each memory cell independently. More sophisticated joint-cell data detection schemes were developed in [5] by introducing pilot cells. However, the probabilistic model in [5] becomes too complex when the array size is getting large. No error correction code (ECC) was employed in previous research works [4][5].
According to the information theory, an efficient way to achieve reliable data storage is to apply ECC to the system. Such a design should not be a straightforward extension of the conventional ECC designed for the symbol-wise independent and identically distributed (i.i.d.) channels. Other than the channel noise, the code must overcome the sneak-path interference which is data-dependent and also correlated within the crossbar array.
In this paper, we propose efficient coding and decoding schemes for ReRAM channels. To reduce the correlation of the sneak-path interference within a codeword, we propose an across-array coding strategy which spreads a codeword to multiple independent memory arrays, and also exploit a real-time channel estimation scheme to obtain the channel status of each memory array. Since the coded bits from different memory arrays experience independent channels, the overall channel will be averaged and a “diversity” gain will be obtained during decoding. In this way, we can design the coding scheme over a symbol-wise i.i.d. channel. By further applying the treating-interference-as-noise (TIN) decoding, the ReRAM channel is equivalent to a block-varying channel whose status does not depend on the input data, based on which we derive the lower and upper bounds of its channel capacity and propose a coding scheme. The proposed coding scheme consists of an outer irregular repeat-accumulate (IRA) code being concatenated with an inner data shaper, which is used to change the input data distribution so as to achieve the maximum information rate. A low-complexity joint message-passing decoding for the IRA code and the data shaper is developed based on the state-of-the-art sparse-graph coding theory. With an optimized IRA code, our ReRAM system achieves a near capacity limit storage efficiency.
The rest of this paper is organized as follows. In Section II, we present the ReRAM channel model and describe the data-dependent feature of the sneak-path interference. The across-array coding strategy and the capacity bounds for the ReRAM channel are proposed in Section III. In Section IV, we propose a coding scheme for ReRAM channels and present both numerical and simulation results. In Section V, we conclude the paper.
II ReRAM Channel Model
Consider an crossbar memory array. The memristor that lies at the intersection of row and column denotes memory cell . Each array is able to store an binary data matrix , where bit is stored in memory cell . During the writing process, each bit is written into the memory cell by changing the resistance value of the memristor, i.e., for a logical “0” bit, the cell is changed to a high resistance of , referred to as the High-Resistance State, and for a logical “1” bit, it is changed to a low resistance of , referred to as the Low-Resistance State.
During the reading process, the data bit can be detected by measuring the resistance value of the corresponding cell. If it is in the High-Resistance State, the bit is identified as a ‘0’; if it is in the Low-Resistance State, the bit is identified as a ‘1’. However, due to the existence of the sneak-path interference, as well as a mix of other noises which can be modeled as an additive Gaussian noise, the memory reading becomes unreliable [3, 4, 5]. When the cell in a memory array is read, certain voltage is applied to the target cell to measure its resistance. A sneak path is defined as a closed path that originates from and returns to location while traversing logical-1 cells through alternating vertical and horizontal steps. An example is shown in Fig. 1, where is a target cell for reading and the green line shows the desired path to measure the resistance. However, forms a sneak path (red line) in parallel of the selected cell . Since sneak paths always degrade the measured resistance value, they actually benefit the data detection when a cell in a Low-Resistance State (logic 1) is read. The detrimental effect only occurs when a High-Resistance State cell (logic 0) is read, making it more vulnerable to noise. In this paper, we only consider the sneak path when a High-Resistance State cell is read.

The most popular method to mitigate the sneak-path interference is to introduce a cell selector in series to each array cell. A cell selector is an electrical device that allows current to flow only in one direction across the cell. Since sneak paths inherently produce reverse currents in at least one of the cells along the parallel path, the cell selector can completely eliminate sneak paths from the entire array. In this paper we follow the previous work [4, 5] and consider the 1D1R structure, even though our proposed approaches can be extended to other structures as well. Although cell selectors can effectively eliminate sneak paths, they are also prone to failures due to the imperfections in the production or the maintenance of memory array, leading to the reoccurrence of the sneak paths. Following previous work [4, 5], we assume that the selectors in a memory array fail i.i.d. with probability . However, our work is based on the fact that once a selector fails it will by no means recover, and hence the locations of the failed selectors are fixed during the reading of the whole array. This is different from the assumption made by the previous work [4, 5] that the locations of the failure cells vary randomly in the crossbar array during the reading of each cell. Although these two assumptions may not affect the detection performance significantly for the uncoded ReRAM systems, they are fundamentally different for the coded systems. The previous assumption [4, 5] actually leads to a near i.i.d. model for the sneak-path interference of each cell. In this work, the sneak-path events for the cells at different locations in the same array are highly correlated, which is much more difficult to be tackled by the channel coding scheme.
We define a sneak-path event indicator for cell to be a Boolean variable with the value if the cell is affected by sneak paths, otherwise, . According to the previous work [5], sneak-path events occur during the reading of cell and lead to if and only if the following three conditions are satisfied:
[Sneak-Path Condition:]
1) The cell is in a High-Resistance State, i.e., .
2) There exists at least one combination of that induces a sneak path, defined by
(1) |
3) The selector at the diagonal cell fails. Due to the circuit structure of the crossbar array, cells and will conduct current in the forward direction and not be affected by their selectors. Only when the selector of the cell is faulty, a sneak path will be formed.
The above Sneak-Path Condition definition limits the sneak path to length of 3, i.e., traversing three cells [5]. More sophisticated cases of the sneak paths were considered in [4]. The principle of our work can be extended to those cases.
Building on the above Sneak-Path Condition, we define a
[ReRAM Channel:]
Let be the stored data array and be the corresponding readback signal for the crossbar array. Let be the set of real numbers. An ReRAM channel is a channel with input and output :
(2) |
where is the parasitic resistance value brought by sneak paths. Here is an additive white Gaussian noise (AWGN) with mean 0 and variance [4]. It is used to model a mix of various noises of the ReRAM system.

The fundamental problem of the ReRAM channel is to recover the stored data array based on readback signal in the presence of sneak-path interference and Gaussian noise . The ReRAM channel with input and output size actually consists of symbol-wise channels with . Since the sneak-path indicator of each target cell is related to the entire data array, these symbol-wise channels are data-dependent and correlated.
The ReRAM channel is also asymmetrical, whose channel status (sneak-path occurring probability) is highly related to the channel input distribution. We define the input distribution as i.i.d. Bernoulli , i.e., and for .
For a fixed input distribution, we investigate the fraction of sneak-path affected cells in the crossbar array and define a sneak-path rate over the array as . Its mean value is derived as a function of :
(4) | |||||
When or is large, (4) is difficult to calculate. However, when is small, using the Taylor expansion , we can approximately calculate (4):
(6) | |||||
where is a balance factor for the last term of the Taylor expansion. Here a good setting for is .
We define the probability mess function (PMF) of the sneak-path rate as
(7) |
For a memory array size of and input distributions with , we simulate and the results are illustrated by Fig. 2. In particular, we generate a large amount of input data arrays, compute the sneak-path rate of each array, and obtain the PMF statistically. In the simulations as well as the numerical results of this paper, we assume the selectors fail i.i.d. with probability . Fig. 2 shows that a larger value of , or a larger array size, leads to higher sneak-path rates, i.e., worse channels. The values of the sneak-path rate are quite diverse for different input data patterns since the PMF spreads in a large range over the abscissa, which indicates that the channel varies significantly for different input data patterns. This is because the occurrence of sneak-path events depends on the input data pattern. This creates a big challenge for designing the coding scheme for the ReRAM channels since the code directly designed based on the average sneak-path rate of will be inadequate.

III Across-Array Coding Strategy and Channel Capacity Bounds
To mitigate the variability of the ReRAM channel, we propose an across-array coding strategy that assigns a codeword to multiple crossbar arrays. Since the coded bits at different arrays experience independent channels, the sneak-path rate within one codeword will be close to its mean value and hence the channel is closer to an i.i.d. channel. Based on the across-array coding strategy, we further investigate the ReRAM channel capacity bounds. As the sneak path is dependent on the data message, it is difficult to derive the exact capacity of the ReRAM channel. By treating the sneak-path interference as the i.i.d. noise during decoding, the ReRAM channel over multiple memory arrays resembles a block-varying channel that we will define in Section III-B, whose status does not depend on the input data. We then derive the capacity bounds of the block-varying channel, which can be regarded as an approximation of the ReRAM channel capacity.
III-A Across-Array Coding Strategy
The proposed across-array coding strategy is illustrated in Fig. 3. Consider the processing of the data vector , where is the code length and is the code rate. Here, is encoded into codeword which is assigned to memory arrays, where for some integer . Thus, we split into equal-length vectors, each of which is assigned to an independent memory array. Without loss of generality, we assign with , to the -th memory array for . Since each memory array is of size , codewords can be stored by these memory arrays, where is assumed to be an integer. As the code rate is , the storage efficiency is bits/cell.
Each codeword is decoded independently based on its readback signal. The codeword is decoded based on its readback signal , where is the readback signal of from the -th memory array, , to obtain the estimated data . Here we employ a suboptimal decoding scheme known as the TIN decoding [6]. The TIN decoder ignores the correlation between the channel input and the sneak paths and treats the sneak-path interference as the i.i.d. noise.
To illustrate the advantage of across-array coding strategy more explicitly, in Fig 4, we evaluate the PMF of the sneak-path rate over one codeword that is stored in memory arrays. In the figure, we employ the array sizes and the code lengths of and . Since the coded bits are distributed in memory arrays, the sneak-path rate as well as its PMF are rewritten as and , where is the sneak-path event indicator during the reading of the -th bit that belongs to the -th array. For each case of and and the given input distribution with and , as increases, the spread of the PMF of the sneak-path rate gets smaller and concentrates closer to the mean value and the channel becomes more stable. The reason is that since the codeword is assigned to independent memory arrays, the sneak-path rate is averaged over the arrays. Based on the law of large numbers, as , the sneak-path rate converges exactly to the mean value with probability 1, and therefore, we can design a code based on this mean value to guarantee error free decoding. Note that the across-array coding strategy does not change the channel correlation. It actually reduces the correlation of the sneak-path interference within one codeword since the readback signals for coded bits from different memory arrays are independent with each other. As all the coded bits are encoded from the same message data, this resembles a “code diversity” strategy for block fading channels [7].

The drawback of a joint coding across arrays is a potential increase of the read/write latency. Note that such additional latency is unavoidable for many sneak-path mitigating approaches in the literature. For example, the multistage reading technique presented in [8] requires three readings and three writings to get a better estimation of the sneak current; [4] investigates the multiple-read detector and shows that it can achieve near-optimum performance with 10 reads. We remark that for our proposed across-array coding strategy, the additional read/write latency can be minimized if a parallel reading/writing circuit [9] is adopted across different crossbar arrays. Moreover, the additional latency incurred will become negligible if the two-dimensional crossbar arrays are stacked to form a 3D structure, which naturally enables the parallel reading/writing across different arrays [10].
III-B Channel Equivalence and Capacity Bounds
We first define a block-varying -channel and show how the ReRAM channel capacity is related to that of the block varying -channel.
To begin, we first define an -channel. As illustrated in Fig. 5, an -channel is a concatenation of an i.i.d. asymmetrical discrete channel and an i.i.d. additive Gaussian channel, and therefore, it is also an i.i.d. channel without channel correlation. The asymmetrical discrete channel is with binary-input and ternary-output from with , and the transition property is described by Pr, Pr, and Pr. The additive Gaussian channel is with noise distribution , whose output serves as the output of the -channel.

For given input distribution Pr, Pr, the -channel capacity can be derived as
where
The - and -channels are asymmetrical binary-input AWGN channels, which are two special cases of an -channel. Obviously, the -channel capacity decreases as increases leading to .
A -block block-varying -channel with parameters varies from data block to data block, while within the -th data block, the channel is a symbol-wise i.i.d. -channel, . The block-varying -channel is a type of channel with block interference as proposed by [11].
The ReRAM channel over memory arrays resembles the -block block-varying -channel. In particular, the sneak-path rate of the ReRAM channel varies from memory array to memory array resembles the block-varying property (the channel varies from block to block) of the block-varying -channel. The channel parameter resembles the instantaneous sneak-path rate of the -th memory array. The main difference is that in the ReRAM channel, the sneak-path interference is dependent on the input data and this data-dependency leads to the channel correlation, while the parameter of block-varying -channel is data-independent and the channel within each block is i.i.d. However, if we adopt TIN decoding where the decoder ignores this data-dependency and regards the sneak paths as the i.i.d. noise, an ReRAM channel is equivalent to a block-varying -channel. The memory block length, denoted by , of the block-varying -channel should be identical to the data array size of the ReRAM channel, i.e., . The channel parameters should be i.i.d. generated based on PMF of the sneak-path rate of the ReRAM channel. Therefore, the maximum achievable coding rate over the ReRAM channel under TIN decoding can be approximated by the block-varying -channel capacity.
In preparation to give the capacity limit, we define an -channel code:
Definition 1
An -channel code includes a sequences of codes with rate and different code lengths , which achieve asymptotical error free decoding over the i.i.d. -channel as the code length approaches infinity.
The existence of the -channel code ensemble is guaranteed by the conventional channel coding theorem.
Consider a block-varying -channel with memory block size . Parameter has the PMF , and mean value , as defined in (4). Since the channel varies from block to block, we consider joint -block encoding and decoding. The code length is therefore . Let be the encoding rate, and we then have the following theorem:
Theorem 1
For fixed input distribution of Bernoulli , as , the maximum achievable code rate with joint -block encoding and decoding is bounded by
(8) |
where .
Proof: We first show that for a fixed input distribution of Bernoulli , is achievable. Let be the joint -block codeword, where -th block experiences an -channel, i.e., each symbol , experiences an i.i.d. -channel. We assume that the codeword is encoded in the way that the -th bits, located at different data blocks, i.e., , belong to a codeword of a length- -channel code. In this way, the original length- codeword can be considered as a vector consisting length- -channel codewords. This is possible because we can always split the uncoded data vector into equal-length sub-vectors, and encode each of them independently using an -channel code. As the encoding rate of each -channel code is , the overall code rate is .
During decoding, for each , is decoded based on its channel output , where is a channel observation of . Since coded bit experiences an -channel, where , are i.i.d. generated based on the PMF of , the overall codeword experiences an -channel where . Since is an -channel codeword, the decoding error probability approaches 0 as according to Definition 1.
In [11], an upper bound of the block interference channel is proposed. That is, given the channel parameters , the channel becomes memoryless, leading to .
It was also shown in [11] that if the channel state is finite, i.e., is from a finite set, the upper bound is tight when the block size .

Based on our channel equivalence, is an approximate lower bound of the ReRAM channel capacity with TIN decoding, and is an upper bound. Since we have the explicit formula (4) for , the lower bound is much easier to be calculated than the upper bound, which requires . Fortunately, we can show that when the array size is large, the two bounds are numerically very close with each other, and hence the lower bound can be a good approximation of the ReRAM channel capacity. Fig. 6 illustrates the capacity upper bound and lower bound as functions of , for different memory array sizes and different noise values of . The resistance parameters are fixed with , and . Observe that when the memory array size is large, the two bounds are very close with each other.
Fig. 6 also indicates that the ReRAM channel capacity bounds decrease as the data size increases due to the increase of the sneak-path rate, i.e., the larger the data array size the lower the average storage efficiency for each cell, and vice versa. For a very low noise level of , the capacity bounds are maximized at about , and for , they are typically maximized when . The optimal value of that maximizes the channel capacity bounds decreases as noise level increases. This is because noise amplifies the detrimental effect of sneak paths, while reducing effectively reduces the sneak-path rate.
IV Design of the Coding Scheme
In this section, we present the design of a coding scheme for the ReRAM channel. We also propose a real-time maximum likelihood channel estimation, based on which the message-passing decoding is performed. We utilize the state-of-the-art sparse-graph code and message-passing decoding theories to design the coding scheme, which is essentially an -channel code design. A major difference between the -channel code and the classical ECC is that since the former works over an asymmetrical channel, the coded data should follow the desired distribution to approach the channel capacity (Fig. 6). We propose a coding scheme, which is a serial concatenation between a classical ECC and a data shaper that shapes the desired data distribution. Bit error rate (BER) simulations and performance comparisons are also presented in this section for our proposed coding scheme.

IV-A Coding and Decoding Model
A system model for the proposed coding scheme is illustrated in Fig. 7. The encoder includes an ECC encoder and a data shaper. The ECC encoder encodes data vector into codeword whose entries are uniformly distributed on . The data shaper reforms the data distribution into Bernoulli . Its output is . Here the data shaper in our system has rate-1, and therefore, the overall code rate is still .
The decoder involves a real-time channel estimator, elementary signal estimator (ESE), a de-shaper, and an ECC decoder. Since the decoding is actually a block-varying -channel decoding, the channel estimator first estimates the channel parameters over the memory arrays based on readback signal . Based on and , the ESE calculates a soft estimation , i.e., the log-likelihood ratio (LLR), for each coded bit that is used as the decoder input. The decoder consists of a de-shaper and an ECC decoder, both of which use soft-in soft-out (SISO) processings and perform iteratively to improve the decoding reliability. The corresponding decoding is standard message-passing decoding. Specifically, the de-shaper calculates soft LLR for each ECC coded bit, based on which an ECC decoding refines the estimation and feds back an updated LLR to the de-shaper for the next round of decoding iterations. After a fixed maximum number of iterations, a hard decision is performed at the ECC decoder to produce data estimation .

IV-B Data Shaper
The data shaper consists of a length- repeater, a length- bit interleaver , and an -to-1 mapper (Fig. 8). The repeater duplicates each ECC coded bit times. The bit interleaver permutes the repeater output to relocate the bits. The -to-1 mapper maps every bits to one bit, i.e., . Therefore, the data shaper’s overall rate is 1. For the -to-1 mapper, since there are patterns for the mapping inputs, by mapping of them to 1 and of them to 0, we obtain the data output with a distribution of Bernoulli . By choosing , we achieve data distributions of Bernoulli with .

The interleaver inside the data shaper is crucial in our scheme. Rather than adopting random interleaving, we propose a structured interleaving scheme, as shown in the data shaper’s factor graph in Fig. 8. The interleaver consists of sub-interleavers , each of which can be random. The data-shaping process can be described using a factor graph. Each variable node is associated with an ECC coded bit, where the -th variable node is associated with . There are edges from a variable node to the interleavers corresponding to the repetitions of the ECC coded bit. Each mapping node has edges from the interleavers corresponding to the mapping inputs. The -th mapping node is associated with the mapping output . By using our structured interleaver, the -th repetitions of the ECC coded bits enter a sub-interleaver whose outputs are used as the -th inputs of the mapping nodes. By doing so, each ECC coded bit has exactly one repetition that occupies the -th input of a mapping node for .
The advantage of employing this structured interleaver can be explained using an example. Consider a data shaper with an -repeater and a 3-to-1 mapper (Fig. 9). There are eight patterns for three binary inputs , where only two of them, 110 and 111, are mapped to 1, and the other six are mapped to 0. If are i.i.d. with Pr=Pr, the mapping can realize output data distribution with Pr, Pr. Next we address the de-mapping. Mapping output actually contains a different quantity of information about the three input bits . By formulating the mapping rule as , where is a multiply operation, we evaluate the mutual information between and each input bit as and . Therefore, if the de-mapper is sufficiently near-optimal, during de-mapping we can obtain information about the first and second bits . Unfortunately, we cannot get any information about the third bit since does not contain any information about . In other words, one-third of the bits are erased after de-mapping. If random interleaving is employed, with probability , all the three repetitions of an ECC coded bit will be assigned as the third input of a mapping node and erased. In other words, with probability , an ECC coded bit will be erased after de-shaping, which leads to a poor ECC decoding performance. Our structured interleaving guarantees that all the ECC coded bits can obtain a positive and statistically equal quantity of information from the de-shaper to benefit the ECC decoding.
IV-C Channel Estimation and ESE
We propose a maximum likelihood channel estimation to obtain parameters . Since the decoder assumes the channel created by the -th memory array as an i.i.d. -channel, with the channel observation of , the log-likelihood function of is written as:
(10) | |||||
Next we consider the approximation for (10). Let be the hard decision value of . Since each term of (10) is in the form of , when the channel noise level is low, it is dominated by the term of . We thereby apply
and hence have the following approximation:
where is the total number of whose hard decision is and is a constant term independent of . By maximizing we obtain the estimation of :
(11) |
Next, the ESE calculates the LLR for each coded bit of based on the readback signal and the estimated channel parameters:
(13) | |||||
for . Note that the implementation of ESE (LABEL:eq:ESE) ignores the correlation between cells in a memory array and regards the sneak-path interference as the i.i.d. noise. A more sophisticated decoding scheme can be developed by utilizing the cell correlation and performing joint data and sneak path detection. It is left as our future work.

To demonstrate the accuracy of the proposed channel estimation, in Fig. 10, we illustrate the mean squared error (MSE) between the estimated and the actual sneak-path rates. We obtain the MSE: by simulation for and memory array sizes , where is the actual sneak-path occurrence rate, and is the estimated value obtained by (11). In general, the MSE is below and decreases as the channel noise level decreases. For comparison, we also illustrate the MSE: between the average and the actual sneak-path rates, where the average sneak-path rate is employed by the decoder when channel estimation is unavailable. Our proposed channel estimation is much more accurate to predict the channel than the average channel parameter, especially for large array size.
IV-D De-Shaper
The SISO de-shaper can also be realized by message-passing processing over the factor graph shown in Fig. 8. During the de-shaping, each node performs as a local processor and the edges pass LLR messages. The message passing on the edges is bi-directional. The overall processing is performed iteratively. In each iteration, each node in the factor graph acts once. A mapping node performs de-mapping processing based on the priori LLRs from its neighboring variable nodes and the LLR from ESE and outputs an extrinsic LLR for each mapping input. The extrinsic LLR is used as an a priori LLR for variable node processings. A variable node combines the priori LLRs from its neighboring mapping nodes and feeds back an extrinsic LLR to each of its neighboring mapping nodes. After a certain number of iterations the variable nodes output a more reliable LLR for each ECC coded bit as the de-shaper output.
IV-D1 Mapping Node Processing
A mapping node represents a mapping constraint, i.e., the edges on the left side link to the variable nodes that are the mapping input, and the edge on the right side links to a mapping output. Therefore, the -th mapping node represents mapping constraint , where are the mapping inputs and is the mapping output. Thus, the edges from the left of a mapping node should pass the LLRs for and the edge from the right side should pass LLR for .
Let be the LLR about , obtained from the ESE. Let be an a priori LLR of from a variable node. The -th mapping node calculates an extrinsic LLR for , given by
where .
IV-D2 Variable Node Processing
Since a variable node is associated with an ECC coded bit, i.e., the -th node is associated with , the edges connected to it should pass LLR messages for the same bit, i.e., , where , are repetitions of .
Consider the processing at the -th variable node. Let be the priori LLR about from the ECC decoder and be the priori LLR about , from the neighboring mapping nodes. Since , the variable node calculates an extrinsic LLR for each , given by
(14) |
After a certain number of processing iterations, the variable node outputs an extrinsic LLR about to the ECC decoder
(15) |
IV-E ECC Optimization and BER Simulations
In this section, we present the ECC optimization and BER simulation results for ReRAM systems. With our proposed ECC, we achieve a high storage efficiency with a gap of less than 0.1 bit/cell from the ReRAM channel capacity.

Array size | ||
---|---|---|
Data shaper | ||
Mapping A | Mapping B | |
IRA code (ECC) | ||
Combiner: | Combiner: | |
Code rate | ||
0.660 | 0.494 |




For the ECC, we adopt an IRA code which is a type of irregular low-density parity-check (LDPC) code that is able to approach the i.i.d. channel capacity with low encoding and decoding complexity [12, 13]. We consider the code design for two ReRAM systems with a memory array sizes of and , and at a noise level of . We adopt the data shapers with a -repeater and 4-to-1 mappers with Mappings A and B (Fig. 11). Mappings A and B produce data distributions of and , respectively, which approach the maximum storage efficiency for the considered ReRAM systems (Fig. 6). Here the maximum storage efficiencies for and ReRAM systems are and bit/cell, respectively. We optimize the IRA code for these two cases over an i.i.d. -channel using a density evolution method [14]. The code parameters for these two ReRAM systems are listed in TABLE I. Our codes achieve and bit/cell, which are close to the capacity bound with gaps of about and bit/cell.
In Figs. 12 and 13, we simulate the BER of the two coded ReRAM systems in TABLE I with the across-array coding strategy over both the ReRAM channels (solid lines) and the equivalent block-varying -channels (labeled by ). Message-passing decoding were employed for both the de-shaper and the ECC decoder, where the decoding of IRA codes can be found [13]. For the system, we employ a code length and for , we adopt . In both figures, the BERs over the ReRAM channels are almost the same as those over the block-varying -channels, thus demonstrating the proposed channel equivalence. The BERs improve as increases and approach the decoding performance over the i.i.d. -channel, which is the performance limit for ReRAM channels as . This performance improvement as increases can be regarded as a “diversity” gain by assigning the codeword to multiple memory arrays. For comparison, we also illustrate the BER performances of the same IRA codes without data shaping over i.i.d. -channel. The decoding performance deteriorates significantly due to the lack of data shaping.
To emphasize the importance of the proposed real-time channel estimation, in Fig. 14, we compared the BERs between the IRA-coded ReRAM channels with and without channel estimation for memory array sizes and joint-coding array numbers . We employ the same code parameters listed in TABLE I for both cases. For the IRA-coded ReRAM channel without channel estimation, we employ the average channel parameter for the decoder. We observe that by applying the channel estimation, the BER improvement is obvious for each comparison pair.
Note that the codes in TABLE I are designed at for the i.i.d. -channel, which means that theoretically the code can be decoded without errors at . However, the actual decoding performances shown in Figs. 12 and 13 are much worse. This is because with density evolution, the code is designed under an infinite code length assumption, while in our simulations finite-length codes were employed. In other words, the codes are asymptotically decodable at as the code length approaches infinity. For the same reason, the ReRAM system achieves a lower BER performance than the system since a much longer code is employed in the system although the codes in both systems are designed at the same noise level of .
In Fig. 15, we provide BER comparisons between our proposed structured interleaving scheme and the random interleaving for the codes in TABLE I over the i.i.d. -channel. For both codes, our proposed structured interleaving scheme outperforms the random interleaving. The BER curves are steeper with structured interleaving than that with random interleaving. This verifies our analysis in Section IV-B. Note that similar performance gain can also be observed from the ReRAM channels, which are the block-varying forms of the -channel.
V Conclusion
We have considered the design of effective channel coding schemes to tackle both the sneak-path interference and the additive noise for the ReRAM channels. We have proposed an across-array coding strategy to mitigate the channel instability. It also enables a “diversity” gain during decoding. By employing TIN decoding, the ReRAM channel is equivalent to a block-varying channel whose status is not data-dependent, based on which, we proposed the capacity limit as well as a coding scheme. We have also proposed a real-time channel estimation scheme to obtain the sneak-path rates of the arrays, based on which an ESE calculates the LLR for each coded bit for decoding. To deal with the channel asymmetry, we proposed an ECC concatenated with a data shaper, where the later forms the desired input data distribution to achieve the maximum information rate. With an optimal ECC design, the ReRAM system achieved a high storage efficiency with a gap of less than 0.1 bit/cell from the ReRAM channel capacity limit.
We would also like to point out some possible extensions that lead to our future work. Although we only considered the AWGN noise in this paper, our work can be easily extended to other types of noises, such as the lognormal noise, through reformulating the channel capacity and the LLR formula in the ESE. Moreover, to consider more general sneak-path models that involve multiple sneak paths affecting a read cell, the channel model in Fig. 5 should be modified as a binary input multi-level output channel, where the types of the output signal levels depend on the corresponding sneak-path combinations [4].
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