Omni 3D: BEOL-Compatible 3D Logic with
Omnipresent Power, Signal, and Clock

IM provides design flexibility with additional intra-cell routing tracks. However, these routing tracks may introduce extra parasitic capacitance. For example, INVs of Omni 3D and Omni 3D without IM (noIM) are illustrated in Fig. 3 (a) and (b), respectively; eliminating IM also removes the via below. Fig. 3 (c) shows input capacitance reduction by $6.7\%$ in noIM. More specifically, IM to the other IM, gate, and S/D capacitance are shrunk. This savings is valid for cells (e.g., INV and BUF) which uses IM as only another via stack.

However, the design impact of IM on complex cells is different from INV/BUFs. We implement $20$ standard cells for Omni 3D, Omni 3D noIM, and CFET. Fig. 4 shows the area benefits of two Omni 3D variants over CFET and the impact of IM to the benefits. The majority of cells save $25\%$ area by cell height reduction, from $4$ tracks to $3$ tracks. Complex cells which demand heavy intra-cell routing (e.g., DFF, XOR, MUX) leverage extra three intra-cell routing tracks in the IM layer to further reduce cell area by shortening cell width in Omni 3D (orange in Fig. 4 (a), See MUX examples in (c) vs. (b)). In contrast, noIM only achieves cell height reduction (green in Fig. 4 (a), See (d) vs. (b)). This is because noIM has the same number of intra-cell routing metal tracks (two each on top and bottom) as CFET (four on top). IM usage for more compact Omni 3D MUX design is shown in Fig. 4 (e) vs. (f).

AOI22 and OAI22 have notable area overhead in Omni 3D noIM. One side of the Omni 3D noIM has only two routing tracks, which are fully occupied by the pins of such a many-input cell, leaving no room for intra-cell routing. Cell width of noIM must therefore be extended to facilitate the necessary intra-cell routing on that side while Omni 3D achieves the routing on the IM layer and avoids cell width extension.

Input and output pin access configurations affect double-side signal routing. Omni 3D with a single-side input and output (SIO) needs two flavors for routing: a top-in (TI) cell and a bottom-in (BI) cell. Fig. 5 (a) depicts a chain of INV cells alternating between TI and BI to opimize routing. However, an arbitrary netlist can easily create a conflict due to multiple fan-in cells (in red) as exemplified in Fig. 5 (b). Thus, such a sequential dependency restricts routing.

Enabling variants of Omni 3D relieve this sequential dependency. One is a double-side input (DI) cell which features duplicated input pins on both sides, and another is double-side output (DO) cell that is characterized by duplicated output pins on both sides. By adding an input pin to the bottom of and an output pin to the top of Fig. 6 (a), respectively, bottom-out (BO) DI (Fig. 6 (c)) and TI DO (Fig. 6 (e)) are formed. From the other flavor of SIO, the corresponding top-out (TO) DI and BI DO are produced (See Fig. 6 (b), (d), and (f)). Any DI cells can be routed by both BO and TO DI drivers as illustrated in Fig. 7 (a), and any DO drivers can route both TI and BI DO cells that follow as presented in Fig. 7 (b). While double-side input and double-side output (DIDO) variants (Fig. 6 (g)) simplify the cell library, it results in excessively many pins on both sides.

We evaluated all four variants of Omni 3D with the same DTCO framework in Section 2, and the minimum-EDP design points are shown in Fig. 8. All variants have similar $R_{eff}$s, $\sim 95\%$ of CFET $R_{eff}$, because their channel widths are equal. Even though DO and DI both adds a pin to one side, the impact on $C_{eff}$ turns out to be different. While adding an extra output pin increases input and output capacitance by $4.2\%$ and $15.8\%$, respectively, adding an extra input pin raises input and output capacitance by $21.8\%$ and $5.8\%$, respectively. In terms of total cell parasitic capacitance, their difference is less than $3\%$ which is diluted by the interconnect capacitance of RO. However, DO and DI showed $5.6\%$ and $11.2\%$ $C_{eff}$ penalties, respectively, compared to SIO. This is because the input capacitance driven at the end of the interconnect has a greater impact on delay than the output capacitance driven in the beginning of the interconnect. Additionally, DIDO has $16.9\%$ more $C_{eff}$ as the sum of DI and DO increases $C_{eff}$ by $(\simeq 5.6\%+11.2\%)$. NoIM results in a $4.4\%$ $C_{eff}$ reduction. Its area benefits in complex cells, however, can only be assessed at the block level.

More importantly, DO always adds only one pin to SIO while DI, in the case of a multi-input cell, needs to place multiple pins which may demand extra design area to ensure intra-cell routing. Considering both $C_{eff}$ benefit and compact design, we choose DO as our optimal Omni 3D for block implementations.

Two key changes in the process development kit (PDK) required to enable double-side routing with commercial EDA tools are: (1) An interconnect technology file (ITF/ICT) and (2) a standard cell layout exchange format (LEF) file. Existing parasitic extraction tools which generate the interconnect RC database (QRC techfile/TLUPlus) only support metal stacks on top of the substrate. Thus, we define bottom-side metal (BM) on top of top-side metal (TM) in reverse order as illustrated in Fig. 9 (a). One extra intermediate layer between TM and BM (i.e., M8) allows block I/O access on both sides but prohibits signal and clock routing to avoid a shortcut between TM7 to BM7. Such a shortcut would imply a vertical path penetrating the whole metal stack. We use predicted $2~{}nm$ technology node metal/via pitches, resistances, and capacitance [29, 30].

Fig. 9 (b) presents pin definitions of BI DO INV in the LEF file. An input pin and output pin on bottom are in BM1, and the other output pin on top is in TM1; vice versa for TI DO INV in Fig. 9 (c). Pins with BM1 and TM1 are routed through BM2 $-$ BM7 and TM2 $-$ TM7, respectively. Consistently, $V_{dd}$ and $V_{ss}$ power rails of each cell are defined on BM1 and TM1, respectively, in the LEF file.

Omni 3D has a split PDN, with $V_{dd}$ on the bottom side and $V_{ss}$ on the top side. We constructed a mirrored PDN on both sides mimicking tight-pitch PDNs known to meet IR drop requirements [31, 32]. This is equivalent to a conventional top-side PDN with densities of $6\%$ and $15\%$ for the lowest and highest routing metal layers, respectively. The split PDN may create inductive loops in the power grid; optimizing the power grid for minimum inductance falls beyond the scope of our study.

Traditional logic synthesis does not anticipate the Omni 3D physical design requirements in three ways. First, the netlist is synthesized to only considering power and delay, and the flavor (i.e., TI or BI) of a cell is arbitrarily determined. Taking the AES256 design as an example, the ratio of TI to BI is $1$:$8$. Using the resulting netlist would both diminish the value of Omni 3D as well as cause significant congestion. This issue can be addressed by balancing the TI and BI cell ratio after synthesis. Fig. 10 shows a decreasing trend of design rule violations (DRVs) as the TI:BI balance improves.

Another aspect is that a logical net can be mapped to two different physical nets as shown in Fig. 11 (a). If an INV (BI) drives two different flavor INVs, a logical net is split into two sides to access the corresponding input pins. However, if either of the load cells is flipped to the other flavor as depicted in Fig. 11 (b), the two physical nets are united on one side eliminating redundant metal usage. Lastly, if two logical nets share a multi-input cell (e.g., ND2 in Fig. 11 (c)), they need to be assigned on the same side. This means that simply balancing the TI and BI cell ratio without considering these characteristics also induces unnecessary routing congestion. In AES256 with simple TI:BI cell count balancing, $6,575$ DRVs remained at the even ratio.

To accommodate the Omni 3D physical design requirements for efficient double-side routing, we modify a netlist after logic synthesis by following Algo. 1. We first identify nets that need to be on the same side and accordingly cluster the relevant cells to be the same flavor. Depth-first search is used to find the cells to cluster. In detail, we start with putting a cell in $cellList$ into an empty cluster. In the function $getSiblingCells$, we obtain the cell’s fan-in nets which must be on the same side, and then list out the sibling cells which are the fan-out cells of those nets. A sibling cell is added to the cluster by a recursive call of the function $clusterCell$, increasing the search depth. Depth drilling ends when no sibling cells are found or the cell of interest is already clustered.

The clusters are then assigned to either a TI or BI flavor, targeting an even ratio of TI to BI. For simplicity, we sort the clusters in descending order by size and assign them alternatively to TI and BI flavors until the number of TI cells exceeds half of the total cell count. Large clusters are thus distributed evenly, with any remaining clusters assigned to BI.

We use the foundation flow [33] with three extra steps. (1) The cell clustering and assignment in Section 4.2 are performed after synthesis, and the updated netlists are loaded by the placer, with the placer using cell clusters for its seed placement. (2) Existing clock tree synthesis (CTS) inserts arbitrary flavors of buffers only considering delay and power, which leads to the clock tree using the prohibited layer (M8). After CTS, therefore, we flip the flavors of clock buffers whose fan-in nets employ M8. (3) Upon completion of detailed routing, we also flip the flavors of buffers in data paths to address potential detoured routes — nets that violate maximum transition time — by the arbitrary-flavor buffer insertion.

In a relaxed target clock period region, as the target decreases, design achieves lower delay without significant impact on energy consumption. Therefore, the EDP trends of AES256 using CFETs and Omni 3D in Fig. 12 (a) are linear until $100~{}ps$; empty symbols are invalid designs but are included to show the trend. The EDP gap between the two libraries is similar to one shown in RO ($1.3\times$ EDP benefits in Omni 3D). However, after $100~{}ps$, CFETs started to include substantially more drivers to attain the target clock period and routing accordingly became more convoluted. However, Omni 3D still had enough routing capabilities. This difference allows delay benefits in Omni 3D physical design over RO. In the comparison of minimum-EDP designs, Omni 3D earned $1.8\times$ EDP and $1.4\times$ area benefits over CFETs simultaneously. Post-PnR layouts of AES256 are in Fig. 12 (b)$-$(d). An even spatial division for the top and bottom side routing is achieved for Omni 3D.

The EDP and area benefits for the all three designs compared to CFETs are summarized in Table 2. Rocket has a small gate count ($\approx 35K$) which can be routed up to TM5 in CFETs, so Omni 3D used up to TM5 and down to BM5. EDP and area benefits of Omni 3D are, respectively, $2.0\times$ and $1.5\times$ on average. Energy benefits are capped by $1.3\times$ while delay benefits vary depending on the congestion level of designs. noIM achieved the same EDP benefits on average while its area was saved by only $1.3\times$ due to the cell-level area penalties appeared in Fig. 4 (a).

We analyze the delay, energy, and area benefits in detail taking AES256 as an example, comparing Omni 3D to CFET and then to noIM.

Delay: Fig. 13 (a) shows the delay breakdown of the top $100$ critical paths of each library. The achieved delay is composed of cell delay, wire delay, setup time of the flip-flop, and clock skew. Before comparison, one notable observation for CFETs is that the wire delay, constituting $39.6\%$ of the total delay, approached that of the cell delay ($47.2\%$). This is attributed to the significant cell resistance improvement of using CNFETs. By introducing Omni 3D, routing congestion was relaxed, hence both wire and driver delays were reduced by $35.0\%$ and $36.0\%$, respectively. noIM showed negligible difference in cell delay from Omni 3D and a $9.0\%$ penalty in wire delay, due to core area increase.

Energy: Energy breakdown is in Fig. 13 (b). With a default logic switching rate, leakage energy is about $1\%$; dynamic energy is decomposed into switching energies and internal energies. Internal energy is estimated from internal power, and switching energy of pins and nets are estimated from switching power in proportion to their capacitances. While cell count is comparable ($1.4\%$ lower in Omni 3D compared to CFET), cell energy — sum of pin switching and internal energy — is lower by $14.9\%$ due to the compact cell design of Omni 3D. More importantly, net switching energy decreased by $24.6\%$ in Omni 3D even though the total wire length is only $11.4\%$ shorter. We attribute the extra net switching energy savings to changes in the wire length distributions across layers (see Fig. 14). M2 of Omni 3D in total is more used than in CFET, but TM2 and BM2 are physically located on two different layers. Thus, metal density of Omni 3D in each layer, which contributes to both ground and coupling capacitance, is reduced.

We observed that intensive use of lower metal layers (M2 and M3) in Omni 3D reduces upper layer metal (M4 and M5) utilization in Fig. 14. Considering the $1.4\times$ area of CFET over Omni 3D, and that both M2 and M3 are similar lengths indicates that Omni 3D relies more on lower metal layers; in other words, CFET is congested in M2 and M3, so some paths are detoured through M4 and M5. noIM has less than $0.1\%$ difference to Omni 3D in total wire length, and its distribution is only slightly different.

Area: To understand the $1.4\times$ area benefits in Omni 3D over CFET, area occupied by each cell in AES256 is normalized by the CFET AES256 total area in Fig 15 (a). CFET bars indicate the area contributions of individual cell. INVD1, ND2D1, NR2D1, and DFF have significant area contributions. Accordingly, area benefits of Omni 3D mainly comes from these cells. Note that while INV, ND, and NR provide only $1.3\times$ area benefit, $1.8\times$ area benefit of DFF is reflected in its large area savings contribution ($14.0\%$). Some other cells (e.g., BUFD1) occupy similar or more area compared to CFET because their cell count increases as presented in Fig. 15 (b).

Fig. 15 (a) shows that DFF area benefits in Omni 3D are decreased in the noIM case vs. IM (due to additional routing flexibility in IM). Another notable impact of IM is that AOI and OAI distributions shift. Due to area-inefficient design of AOI22 and OAI22, their counts are lowered in Omni 3D noIM desgin points compared to Omni 3D designs, and instead, the counts of AOI21 and OAI21 increased to synthesize the same functions. Due to cell-level area increase in a few cells (e.g., DFF, AOI22, and OAI22), AES256 area benefit of noIM was cut to $1.3\times$.