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Non-Hermitian Physics-Inspired Voltage-Controlled Oscillators with Resistive Tuning

Weidong Caoa, Hua Wangb, and Xuan Zhanga aWashington University in St. Louis, Saint Louis, MO, USA; bETH Zürich, Zürich, Switzerland
Abstract

This paper presents a non-Hermitian physics-inspired voltage-controlled oscillator (VCO) topology, which is termed parity-time-symmetric topology. The VCO consists of two coupled inductor-capacitor (LC) cores with a balanced gain and loss profile. Due to the interplay between the gain/loss and their coupling, an extra degree of freedom is enabled via resistive tuning, which can enhance the frequency tuning range (FTR) beyond the bounds of conventional capacitive or inductive tuning. A silicon prototype is implemented in a standard 130130 nm bulk CMOS process with a core area of 0.15mm20.15\text{mm}^{2}. Experimental results show that it achieves a 3.1×3.1\times FTR improvement and 30%30\% phase noise reduction of the baseline VCO with the same amount of capacitive tuning ability.

Index Terms:
Non-Hermitian physics, voltage-controlled oscillator, PT-symmetry, resistive tuning, frequency tuning range.

I Introduction

Inductor-capacitor (LC) voltage-controlled oscillators (VCOs) are the key building blocks in many communication systems [1, 2, 3]. Such local oscillators need to cover a wide frequency tuning range (FTR) and maintain good phase noise (PN) performance. Existing methods mainly rely on aggressive inductive tuning (e.g., negative inductance/switched-inductors) [4, 5] or capacitive tuning (e.g., varactors/switched-capacitors) [6] to reach a wide FTR. However, they often suffer from degenerated PN performance due to the excessive noise sources introduced by the tuning mechanisms. Some techniques have been proposed to tackle the stringent design trade-off between FTR and PN. For example, multi-core and multi-mode VCOs implemented with two or more coupled LC cores can reduce PN and extend the FTR, but bear the cost of excessive design complexity in VCO cores [7, 8]. On the other hand, leveraging multiple separated LC VCOs can extend the FTR, but induces large area overhead and high multiplexing complexity [9]. Therefore, developing more effective approaches to improving the FTR without hurting the PN performance is highly desirable.

Toward the goal, a gain-loss coupled dual-core VCO topology based on non-Hermitian physics is shown in this paper, which is originally proposed in our prior work [10]. From the perspective of non-Hermitian physics, the eigenfrequency of a physical system built upon two coupled units with a balanced gain and loss distribution can evolve in a wide range by tuning the gain/loss contrast [11, 10]. Inspired by this physical principle, we build this gain-loss coupled dual-core VCO. It not only inherits the superior PN performance from the coupled structure of multi-core VCOs but also achieves an enlarged FTR beyond the bounds of conventional capacitive/inductive tuning with extra resistive tuning. The proposed topology can be combined with existing optimization approaches to further advance VCO performance. Section II introduces the theoretical model of non-Hermitian quantum physical systems composed of two coupled units with a balanced gain and loss profile. Circuit design and analysis are presented in Section III. Comprehensive measurement results are shown in Section IV before the conclusion in Section V.

II Background

Refer to caption
Figure 1: (a) Illustration of an open non-Hermitian quantum system that can be modeled as a gain (G) or a loss (L) unit. (b) Illustration of a non-Hermitian quantum system with a coupled gain and loss profile. ω1,2\omega_{1,2} is the resonant frequency of the unit. g-g and ll represents gain and loss amount respectively.

II-A Non-Hermitian Quantum Mechanics

In quantum mechanics, an open system can be generally modeled as a gain (or loss) unit with a resonant frequency as shown in Fig. 1(a). Such systems are described by non-Hermitian Hamiltonians which preserve complex eigenvalues, i.e., ω1ig\omega_{1}-ig or ω2+il\omega_{2}+il. However, non-Hermitian quantum systems built upon two coupled units, one with gain and the other one with loss as shown in Fig. 1(b), possess purely real eigenfrequencies in certain regimes as derived below. Note that such systems are also specifically termed parity-time-symmetric (PT-symmetric) systems [10]. The system dynamics in Fig. 1(b) is expressed as

ddt[aGaL]=[iω1+gκκiω2l][aGaL],\dfrac{d}{dt}\left[\begin{array}[]{c}a_{\text{G}}\\ a_{\text{L}}\\ \end{array}\right]=\left[\begin{array}[]{cc}i{\omega_{1}}+g&\kappa\\ \kappa&i{\omega_{2}}-l\\ \end{array}\right]\cdot\left[\begin{array}[]{c}a_{\text{G}}\\ a_{\text{L}}\\ \end{array}\right], (1)

where the subscript G (or L) refers to the gain (or loss) unit and aG,La_{\text{G,L}} is the field amplitude defined such that |aG,L|2|a_{\text{G,L}}|^{2} represents the energy stored in each unit. gg (or ll) presents the gain (or loss) of the unit. κ\kappa indicates the coupling strength between the two units and ω1,2\omega_{1,2} represents the resonant frequency of each unit. To find the eigenfrequencies, we let aG,Lexpiωta_{\text{G,L}}\propto{\exp^{i\omega t}} and obtain the characteristic equation as

(i(ω1ω)+g)(i(ω2ω)l)+κ2=0.\big{(}i(\omega_{1}-\omega)+g\big{)}\cdot\big{(}i(\omega_{2}-\omega)-l\big{)}+{\kappa}^{2}=0. (2)

For a balanced system where the gain is equal to the loss, i.e., g=lg=l, the solutions are then given by the following expression:

ω=ω0±κ2g2,ω0=(ω1+ω2)/2.\omega=\omega_{0}\pm\sqrt{{\kappa}^{2}-g^{2}},~{}\omega_{0}=(\omega_{1}+\omega_{2})/2. (3)

Eq. (3) shows that when the coupling strength κ\kappa is stronger than a threshold determined by the gain-loss contrast gg, i.e., κ>g=l\kappa>g=l, the system has a pair of real eigenfrequencies. Particularly, these eigenfrequencies could evolve with gain-loss contrast in a wide range as long as g=l(0,κ)g=l\in(0,\kappa). This simple analysis suggests that the interplay between gain/loss and their coupling provides a new degree of tuning freedom, i.e., gain/loss tuning freedom, to modulate the behaviors of a system. In the next section, we discuss how this physical principle (i.e., PT-symmetric topology) can be applied to design VCOs.

Refer to caption
Figure 2: Structure comparisons between (a) conventional single-core VCOs, (b) multi-core VCOs, and (c) proposed VCOs. (d) Numerical comparisons of frequency tuning between the three types of VCOs.

II-B Non-Hermitian Quantum Mechanics for VCO Design

Before introducing the proposed VCO topology, Fig. 2 first re-examines conventional single-core and multi-core VCOs. A single-core VCO can be simplified into an active LC resonator shown in Fig. 2(a). It consists of a gain (R-R) and an LC core with an intrinsic loss (R0R_{0}). A multi-core VCO (e.g., dual-core) is built upon two coupled single-core VCOs with a fixed coupling strength κ\kappa, each of which is simplified into an active LC resonator. For both VCOs, at the start-up phase, the gain is set to be slightly higher than the inherent loss to produce an oscillation with exponentially-growing amplitude. As the amplitude grows, the gain saturates and equates the loss in the large-signal domain due to nonlinearity. The oscillation then becomes stable, and the frequency (i.e., ωS/ωM\omega_{\text{S}}/\omega_{\text{M}} in Fig. 2(a)/(b)) can only be adjusted via ω0\omega_{0} by tuning the core’s capacitance or inductance. In particular, the multi-core VCO has two frequency modes as shown by ωM\omega_{\text{M}} in Fig. 2(b).

This re-examination shows that in the conventional VCOs, the gain-loss distribution plays only a trivial role in the transient behavior of oscillators, i.e., the gain is used to compensate for the undesired loss to establish the start-up condition for the exponential growth of oscillation amplitude. Fortunately, based on the non-Hermitian quantum mechanics introduced before, the loss is useful if the gain-loss distribution in a system is properly manipulated. Inspired by this physical principle, our method explores the interplay between the gain/loss distribution and their coupling to enhance the frequency tuning bandwidth of VCOs. Fig. 2(c) exhibits the simplified topology of the proposed VCO. It is built upon two coupled LC cores, one active with a negative resistance g-g and the other one dissipative with an equal amount of loss ll, and the two cores have the same capacitance and inductance. The proposed VCO exhibits two frequency modes as shown by ωP\omega_{\text{P}} in Fig. 2(c) and an extra resistive tuning freedom (i.e., gg) that is orthogonal with the typical capacitive/inductive tuning freedoms of ω0\omega_{0}. Fig. 2(d) numerically compares the frequency tuning of these three types of VCOs. Both the single-core VCO and multi-core VCO have only individual frequency points (i.e., blue circle and red asterisks), which are independent of gg. However, the proposed VCO has a very wide FTR enabled by gg. The comparison shows that the proposed VCO with the resistive tuning freedom can achieve a wider FTR than conventional VCOs given the same capacitive/inductive tuning ability preserved by ω0\omega_{0}.

III Gain-Loss Coupled Dual-Core VCO Topology

Refer to caption
Figure 3: The circuit schematic of the proposed VCO.

III-A Circuit Design

Fig. 3 shows the proposed VCO circuit. The gain side has a tunable gain rate generated by cross-coupled differential pairs (XDPs) and an inherent loss rate RG0R_{\text{G0}}, leading to the total gain of RG=(1/Gm)||RG0-R_{\text{G}}=(-1/G_{m})\verb||||R_{\text{G0}}; Gm=(gmn+gmp)/2G_{m}={(g_{\text{mn}}+g_{\text{mp}})/{2}}, where gmng_{\text{mn}} and gmpg_{\text{mp}} are the small signal transconductance of NMOS and PMOS XDP. The loss side has an intrinsic loss rate RL0R_{\text{L0}} and a variable loss rate RL1R_{\text{L1}}, giving the total loss of RL=RL0||RL1R_{\text{L}}=R_{\text{L0}}\verb||||R_{\text{L1}}. To make loss adjustable, a variable resistor based on stacked transistors is parallelly connected to the loss side. The subset in Fig. 3 shows the schematic of the variable resistor RL1R_{\text{L1}}. All the gates of MOSFETs are connected together. By tuning the gate voltage VBIASLV_{\text{BIASL}}, the resistance can be continuously adjusted in a wide range. The capacitor CGC_{\text{G}} (CLC_{\text{L}}) in each LC core is composed of a parasitic capacitance CG0C_{\text{G0}} (CL0C_{\text{L0}}), a fixed Metal-Insulator-Metal (MIM) capacitor CG1C_{\text{G1}} (CL1C_{\text{L1}}) with high-quality factor (high-Q) and an adjustable varactor CG2C_{\text{G2}} (CL2C_{\text{L2}}). The varactor takes up a small proportion of the total capacitance and is mainly used to compensate for the fabrication mismatch of the fixed MIM capacitors on each side. The coupling capacitance (CCC_{\text{C}}) is realized by two equal MIM capacitors (CC1C_{\text{C1}} and CC2C_{\text{C2}}) which are serially connected through an on-chip switch (SW). The inductance (LG/LLL_{\text{G}}/L_{\text{L}}) in both cores comes from the high-Q symmetrical parallel inductor (symindp) of the technology. A center tap connection is provided such that both cores share the same common mode voltage by connecting the center taps of the inductors. The balanced condition is satisfied by setting RGRL=RR_{\text{G}}\approx R_{\text{L}}=R, LGLL=LL_{\text{G}}\approx L_{\text{L}}=L, and CGCL=CC_{\text{G}}\approx C_{\text{L}}=C.

III-B Phase Noise Analysis

We perform a qualitative analysis on the phase noise (PN) of the proposed VCO. It is well-established in the classic VCO theory that a multi-core VCO built upon a coupled structure can lead to PN reduction as compared to a single-core VCO. By taking a two-core VCO as an example, the improved PN can be intuitively understood as that the equivalent current noise of each LC core experiences twice the capacitance, and therefore its PN contribution is reduced by 66 dB. Two noise contributions from the two cores are uncorrelated and can be summed up, ideally leading to a 33 dB reduction of the total PN. Generally, for an NN-core VCO built upon a coupled structure, its PN is lower than a single-core VCO by 10log10N10\log_{10}N dB. Thanks to the coupled structure, the proposed VCO topology also inherits the PN advantage of conventional multi-core VCOs. On the other hand, the gain-loss tuning physically realized by active devices, although it does not generate more inherent losses, does contribute additional noise to the system. However, this is not a big issue as the unique gain-loss tuning also increases the carrier amplitude which suppresses the effect of noise. It can be shown as follows. For the proposed VCO, the gain not only compensates the inherent loss in the active core but also offsets the tunable loss in the coupled lossy core. Assuming the ratio between the tunable gain Gm-G_{m} generated by XDPs and the inherent loss R0R_{0} is β\beta (β>1\beta>1), the PN of the active core in our proposed VCO can be obtained based on the well-known PN model of single-core VCOs as below:

P(ω)= 10log10((1+βm)4kTR0(β2Vosc)2(ω2QSω)2)=10log10((1+m)4kTR0(Vosc)2(ω2QSω)2)S(ω)10log10(β4(1+m)(1+βm))>0<S(ω),\begin{split}&\ \mathcal{L}_{\text{P}}(\triangle\omega)=\\ &\ 10\log_{10}\Bigg{(}(1+\beta m)\cdot\frac{4kTR_{0}}{({\beta}^{2}V_{\text{osc}})^{2}}\cdot\Big{(}\frac{\omega}{2Q_{S}\triangle\omega}\Big{)}^{2}\Bigg{)}\\ &\ =\underset{\mathcal{L}_{\text{S}}(\triangle\omega)}{\underbrace{10\log_{10}\Bigg{(}(1+m)\cdot\frac{4kTR_{0}}{(V_{\text{osc}})^{2}}\cdot\Big{(}\frac{\omega}{2Q_{S}\triangle\omega}\Big{)}^{2}\Bigg{)}}}\\ &\ -\underset{>0}{\underbrace{10\log_{10}\Big{(}\dfrac{{\beta}^{4}(1+m)}{(1+\beta m)}\Big{)}}}<\mathcal{L}_{\text{S}}(\triangle\omega),\end{split} (4)

where kk is the Boltzmann constant; TT is the absolute temperature; R0R_{0} is the inherent resonator loss; mm (m>1m>1) is a constant noise factor of active elements; VoscV_{\text{osc}} is the amplitude of the carrier; QSQ_{S} is the quality factor of the LC core; S(ω)\mathcal{L}_{\text{S}}(\triangle\omega) is PN of a conventional single-core VCO. Compared to the PN of conventional single-core VCOs, both the noise factor mm of active devices and the amplitude VoscV_{\text{osc}} of carrier increase in the PN formula of the active core of the proposed VCO. But the carrier amplitude increases to β2×\beta^{2}\times of the conventional one because the current flowing into the core is quadratically proportional to the gain when XDPs operate in the saturation region. Therefore, the proposed VCO topology shows better PN performance than conventional single-core VCOs.

IV Experimental Evaluations

To experimentally verify the advantages of the proposed VCO, a prototype design is implemented in a standard 130130 nm bulk CMOS process with a core area of 0.150.15 mm2\text{mm}^{2} as shown in Fig. 4. The two LC cores can be coupled (decoupled) by turning on (off) the switch SW. A single-core VCO, i.e., the active LC core in our design, is used as the baseline to directly compare with ours on the same monolithic chip. The baseline only has capacitive tuning freedom. Additionally, since it inherently comes from our proposed VCO with the same non-ideal parasitic effects, thereby serving as a fair candidate for comparison to show the enhanced performance solely due to the contribution of the extra resistive tuning freedom.

Refer to caption
Figure 4: Die micrograph of the proposed VCO.
Refer to caption
Figure 5: Frequency tuning of the two VCOs. (a), The baseline VCO. (b), The proposed VCO. Theory: theoretical predictions; Exp: experimental results.
TABLE I: Comparisons between the proposed VCO and state-of-the-art VCOs.
Reference JSSC ’13 [6] TCAS-I ’12 [4] ISSCC ’19 [12] ISSCC ’19 [7] JSSC ’17 [8] This work
VCO types Single-core Single-core Single-core Dual-core Quad-core Dual-core
Optimization technique
Suppression of
flicker noise
Switched-coupled inductor,
aggressive capacitive tuning
Narrowband
resonance at 2fosc2f_{\text{osc}}
Aggressive
capacitive tuning
Multi-core
No
optimization
Technology 6565 nm CMOS 9090 nm CMOS 2222 nm FDSOI 6565 nm CMOS 5555 nm BiCMOS 130130 nm CMOS
Power supply (V) 1.21.2 1.21.2 0.150.15 0.650.65 1.21.2 1.21.2
Power (mW) 0.720.72 1.061.06 0.911.220.91\sim 1.22 17.521.617.5\sim 21.6 5050 24.312\sim 4.31
Area (mm2)\text{mm}^{2}) 0.08060.0806 0.50.5 0.2720.272 0.080.08 0.60.6 0.150.15
Tuning bandwidth (GHz) 3.03.63.0\sim 3.6 1.131.91.13\sim 1.9 4.154.974.15\sim 4.97 253825\sim 38 17.420.317.4\sim 20.3 2.633.202.63\sim 3.20
FTR (%) 18.2%18.2\% 50.8%50.8\% 18%18\% 41.2%41.2\% 15.3%15.3\% 20.2%20.2\%
Resistive tuning
PN (dBc/Hz) (Average) 112-112@11MHz 117.2-117.2@11MHz 141-141@1010MHz 116-116@33MHz 106.5-106.5@11MHz -120.3120.3@11MHz
FoM (dB)a  (Average) 183183@11MHz 177.3177.3@11MHz 193193@1010MHz 183183@33MHz 187.5187.5@11MHz 184184@11MHz
FoMT\text{FoM}_{\text{T}} (dB)b  (Average) 188.2188.2@11MHz 191191@11MHz 198198@1010MHz 195195@33MHz 191191@11MHz 190.1190.1@11MHz
  • a

    FoM=|PN|+20log10(fosc/f)10log10(PDC/1mW)\text{FoM}=|{\text{PN}}|+20{\log}_{10}(f_{\text{osc}}/\triangle f)-10\log_{10}(P_{\text{DC}}/1\text{mW}).

  • b

    FoMT=FoM+20log10(FTR/10%)\text{FoM}_{\text{T}}=\text{FoM}+20\log_{10}({\text{FTR}}/10\%).

Fig. 5 shows the frequency tuning curves of the two VCOs. The baseline yielded a 0.200.20 GHz (3.033.233.03\sim 3.23 GHz, 6.4%6.4\% FTR) bandwidth tuning as demonstrated in Fig. 5(a) by adjusting the control voltage of varactors. Such a tuning range corresponds to a capacitive tuning ability of [1.30,1.50][1.30,1.50] pF. We then set the core capacitance to be 1.351.35 pF and 1.451.45 pF respectively. Fig. 5(b) exhibits the tuning curves corresponding to each capacitance value. At C=1.35C=1.35 pF (C=1.45C=1.45 pF), the proposed VCO achieves a tuning bandwidth of [2.77,3.20][2.77,3.20] GHz ([2.63,2.98][2.63,2.98] GHz) with the extra resistive tuning freedom. The results show that even with a slightly reduced amount of the capacitive tuning ability, the proposed VCO can realize a wider bandwidth tuning of 0.570.57 GHz (2.633.202.63\sim 3.20 GHz, 20.2%20.2\% FTR) by including the resistive tuning freedom, enabling a 3.1×3.1\times FTR of the baseline. Note that this prototype only a small range of capacitive tuning ability (i.e., [1.30,1.50][1.30,1.50] pF) is included in this prototype, thereby achieving an FTR of 20%20\%. By slightly increasing the capacitive tuning ability, the proposed VCO can readily realize a wider FTR.

Refer to caption
Figure 6: PN comparisons of two VCOs across different oscillation frequencies.

We then show the PN of both VCOs. Particularly, we measure the PN at three frequency points for each VCO in its tuning bandwidth. For the proposed VCO, we choose such frequencies to be 2.842.84 GHz (low), 3.043.04 GHz (medium), and 3.223.22 GHz (high). While for the baseline VCO, we choose them to be 3.053.05 GHz (low), 3.123.12 GHz (medium), and 3.223.22 GHz (high). Fig. 6 shows the measured PN at 11 MHz offset frequency for the two VCOs. We observed that the PN of the proposed VCO is generally 1.51.5 dB better than the baseline across the different oscillation frequencies. Due to the parasitics of the switch connecting the two LC cores, the PN improvement is not as much as the ideal case discussed in Section III-B. However, these observations generally match well with the previous qualitative characterizations. Our results show that manipulating the gain-loss profile and their coupling provides a new method to extend the frequency tuning dimension beyond conventional capacitive/inductive tuning without compromising the PN performance for VCO design.

Additionally, we compare the proposed VCO with other conventional VCOs, i.e., single-core VCOs, two-core VCOs, and quad-core VCOs that employ different tuning manners or coupling structures, as summarized in Table I. These conventional VCOs exploit different optimization techniques, such as aggressive capacitive tuning to reach wide FTR (TCAS-I ’12 [4]), narrow band resonance at 2fosc2f_{\text{osc}} to boost PN performance (ISSCC ’19 [12])), and multi cores to enhance PN performance (JSSC ’17 [8]). However, our proposed VCO only includes a resistive tuning into design without any other optimization techniques. The comparison still shows its comparable FTR, PN, and figure-of-merit (FoM) with these prior arts. In summary, the resistive tuning of our proposed VCO topology is orthogonal with other capacitive/inductive tuning dimensions to enhance the performance of VCOs with diverse conventional topologies and optimization techniques.

V Conclusion

A non-Hermitian physics-inspired topology of VCO is shown in this paper. The new topology enhances the FTR of existing VCOs with extra resistive tuning freedom. A prototype is implemented in a standard 130130 nm CMOS process to demonstrate its advantages. The comparisons show that the resistive tuning of our proposed VCO topology is orthogonal with other capacitive/inductive tuning dimensions to enhance the performance of VCOs with diverse conventional topologies and optimization techniques. Future explorations can be performed by cascading multiple such VCOs in a one-dimensional chain similar to the one shown in prior work [13], which may also achieve topological oscillators.

References

  • [1] F. Lv, X. Zheng, F. Zhao, J. Wang, S. Yue, Z. Wang, W. Cao, Y. He, C. Zhang, H. Jiang, and Z. Wang, “A power scalable 2-10FIX ME!!!!Gb/s PI-based clock data recovery for multilane applications,” Microelectronics Journal, vol. 82, pp. 36–45, 2018.
  • [2] N. Zhou, L. Wu, Z. Wang, X. Zheng, W. Cao, C. Zhang, F. Li, and Z. Wang, “A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology,” in 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 2016, pp. 1–4.
  • [3] W. Cao, Z. Wang, D. Li, X. Zheng, K. Huang, S. Yuan, F. Li, and Z. Wang, “A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS,” in 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).   IEEE, 2015, pp. 1–4.
  • [4] A. I. et al, “A 1-mW 1.13–1.9 GHz CMOS LC VCO Using Shunt-Connected Switched-Coupled Inductors,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 6, pp. 1145–1155, 2012.
  • [5] Tanabe, Akira et al, “A 5–20GHz tunable LC-VCO using variable bridge inductor,” in 2010 Symposium on VLSI Circuits, 2010, pp. 47–48.
  • [6] F. Pepe, A. Bonfanti, S. Levantino, C. Samori, and A. L. Lacaita, “Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band,” IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2375–2389, 2013.
  • [7] A. Bhat and N. Krishnapura, “26.3 A 25-to-38GHz, 195dB FoMT\text{FoM}_{\text{T}} LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios,” in 2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, pp. 412–414.
  • [8] L. Iotti, A. Mazzanti, and F. Svelto, “Insights Into Phase-Noise Scaling in Switch-Coupled Multi-Core LC VCOs for E-Band Adaptive Modulation Links,” IEEE Journal of Solid-State Circuits, vol. 52, no. 7, pp. 1703–1718, 2017.
  • [9] W. Deng, H. Jia, R. Wu, S. Sun, C. Li, Z. Wang, and B. Chi, “An 8.2-to-21.5 ghz dual-core quad-mode orthogonal-coupled vco with concurrently dual-output using parallel 8-shaped resonator,” in 2021 IEEE Custom Integrated Circuits Conference (CICC), 2021, pp. 1–2.
  • [10] W. Cao, C. Wang, W. Chen, S. Hu, H. Wang, L. Yang, and X. Zhang, “Fully integrated parity–time-symmetric electronics,” Nature nanotechnology, vol. 17, no. 3, pp. 262–268, 2022.
  • [11] Ş. K. Özdemir, S. Rotter, F. Nori, and L. Yang, “Parity–time symmetry and exceptional points in photonics,” Nature Materials, vol. 18, no. 8, pp. 783–798, Aug 2019.
  • [12] O. El-Aassar and G. M. Rebeiz, “26.5 A 0.1-to-0.2V Transformer-Based Switched-Mode Folded DCO in 22nm FDSOI With Active Step-Down Impedance Achieving 197dBc/Hz Peak FoM and 40MHz/V Frequency Pushing,” in 2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, pp. 416–418.
  • [13] Y. Liu, W. Cao, W. Chen, H. Wang, L. Yang, and X. Zhang, “Fully integrated topological electronics,” Scientific reports, vol. 12, no. 1, p. 13410, 2022.