Modularized Control Synthesis for Complex Signal Temporal Logic Specifications
Abstract
The control synthesis of a dynamic system subject to a signal temporal logic (STL) specification is commonly formulated as a mixed-integer linear/convex programming (MILP/ MICP) problem. Solving such a problem is computationally expensive when the specification is long and complex. In this paper, we propose a framework to transform a long and complex specification into separate forms in time, to be more specific, the logical combination of a series of short and simple subformulas with non-overlapping timing intervals. In this way, one can easily modularize the synthesis of a long specification by solving its short subformulas, which improves the efficiency of the control problem. We first propose a syntactic timing separation form for a type of complex specifications based on a group of separation principles. Then, we further propose a complete specification split form with subformulas completely separated in time. Based on this, we develop a modularized synthesis algorithm that ensures the soundness of the solution to the original synthesis problem. The efficacy of the methods is validated with a robot monitoring case study in simulation. Our work is promising to promote the efficiency of control synthesis for systems with complicated specifications.
I INTRODUCTION
Signal temporal logic (STL) is widely used to specify requirements for robot systems [1, 2], due to its advantage in specifying real-valued signals with finite timing bounds [3]. System control with STL specifications renders a synthesis problem that can be solved by mixed integer linear/convex programming (MILP/MICP) [3, 4]. Based on this a closed-loop controller can be developed using model predictive control (MPC) [5, 6]. However, solving a MILP/MICP problem is computationally expensive and time-consuming, especially for complex STL formulas with long timing intervals since the computational load grows drastically as the number of the integer variables increases (exponentially in the worst case) [7]. Thus, computational complexity has become a bottleneck of the control synthesis of complex STL specifications, especially those with time-variant specifications [8] and fixed-order constraints [9]. One effective approach is the model-checking-based method which transforms an STL formula into an automaton with strict timing bounds [10]. This method is usually less complex than an optimization problem since it is only concerned with a feasible solution. Control barrier functions (CBF) [9] and funnel functions [11] are also used to simplify the STL synthesis problems.
Another direction of reducing the complexity is to decompose a long and complex STL formula into several shorter and simpler subformulas and solve them sequentially. A subformula refers to a simple STL formula that serves as a primitive unit of a complex formula [12]. This indicates the possibility of splitting a big planning problem into several smaller problems and solving them one by one in the order of time, which forms the essential thought of modularized synthesis. This idea is straightforward from a practical perspective: a complex task is usually composed of a series of smaller subtasks that have independent objectives and are ordered in time. For example, a typical food delivery task includes three subtasks: picking up the order at the restaurant, navigating to the customer, and performing the delivery. Finishing these subtasks means accomplishing the overall task. The advantage of this approach is based on the assumption that solving a subtask may be substantially simpler than directly solving the original overall task.
However, modularized synthesis based on specification decomposition is not trivial and brings up two major challenges. Firstly, the decomposed specification has to ensure soundness, i.e., any feasible solution of the modularized synthesis must also be a feasible solution of the original specification. This is important to ensure the efficacy of the specification decomposition and modularized synthesis [13]. Secondly, the subformulas may have overlapping timing intervals which indicate the dependence coupling among these subformulas. In this case, each subformula should not be synthesized independently but should incorporate the coupling with its overlapping subformulas. In existing work, the soundness of specification separation is ensured by syntactic separation as partially discussed in [14, 15]. Recently, model checking based on specification decomposition has been studied for a fragment of STL formulas [16]. Nevertheless, the coupling issues among subformulas have not been well resolved by the existing work. To our knowledge, there is no other existing work discussing the modularized synthesis of STL formulas, although we believe it to be a promising technology for the efficient synthesis of complex specifications.
In this paper, we investigate the modularized synthesis of complex STL specifications based on timing separation. We specifically look into a fragment of STL formulas composed of complex temporal operators for which interval overlapping can not be resolved by purely using syntactic separation. Besides proposing several complementary syntactic separation principles to the existing work [14, 15], we also provide a sufficient separation method for this STL fragment with the overlapping between subformulas eliminated. In such a way, we develop a modularized synthesis algorithm for the separated specification by transforming the overall synthesis problem into several small planning problems with reduced complexity, achieving higher efficiency than directly solving the original problem. The main contributions are as follows.
1). Proposing a syntactic timing separation form of a fragment of STL formulas that is proven to be syntactically equivalent to the original specification.
2). Proposing a complete splitting form of this STL fragment which is proven to be sound in semantics.
3). Developing a modularized synthesis algorithm for the complete splitting form, which ensures soundness but less complexity than the original specification synthesis problem.
The rest of the paper is organized as follows. Sec. II introduces the preliminary knowledge of this paper. In Sec. III, we present our main results on specification separation and modularized synthesis. Sec. IV provides a simulation case study to validate the efficacy of the proposed modularized synthesis method. Finally, Sec. V concludes this paper.
Notations: We use and to denote the sets of real scalars and -dimensional real vectors. We also use and to denote natural numbers and positive natural numbers.
Proofs: All proofs of this paper are in the Appendix.
II Preliminaries and Problem Statement
II-A Signal Temporal Logic (STL)
Specifications in Signal Temporal Logic (STL) can quantify requirements on real-valued signals. In this paper, we are concerned with discrete-time signals , where denotes the length of the signal and is the value of the signal at time . With , we denote a segment of or equivalently with timing points . The syntax of STL is recursively defined as
(1) |
where are STL formulas, , are operators negation and conjunction, is a predicate that evaluates a predicate function by , for discrete time , and is the until operator bounded with time interval , where and .
The semantics of STL are given as follows. We denote the satisfaction of at time by as . Furthermore, we have that ; ; and ; , such that , and holds for all . Besides, additional operators disjunction, eventually, and always are, respectively, defined as , , and . When , we also write as . The length [17] of an STL, , is recursively defined as , , , , which represents the maximum time it takes to determine the truth of the formula .
II-B Optimization-Based Specification Synthesis
STL formulas are used to specify the requirements of a signal of a dynamic system. In this paper, we consider the following discrete-time dynamic system,
(2) |
where and are the state and the control input of the system at time , where is the admissible control set, and is a smooth vector field. Then, the control problem of the system can be formulated as the following optimization problem,
(3a) | ||||
(3b) |
where is the control horizon, and are the open-loop control and state signals, is an STL formula with to specify the requirements on the state signal , and is the robustness of the satisfaction as defined in [18, 19], with . Eq. (3) renders an open-loop control problem and can be solved using MICP [7] with an input interface .
II-C Problem Statement
Solving problem (3) using MICP usually introduces heavy computational load due to the large number of integer variables brought up by the logical and temporal operators in the specification [7]. Usually, longer formulas introduce substantially more integer variables than shorter ones. In the worst case, a specification may contain or subformulas with the same length . This requires binary variables to determine the logical satisfaction of the complete specification, which leads to an exponential complexity . Therefore, the computational complexity of the synthesis problem is greatly dependent on the number and the lengths of subformulas.
In this paper, we intend to reduce the complexity of a synthesis problem (3) by separating a long specification into shorter subformulas which can be solved by smaller optimization problems. Examples of such separation include the following principle for an until operator with a separating point , [14],
(4) |
where the temporal operators and in (4) have shorter intervals compared to the original interval . This form is referred to as syntactic separation since it ensures syntactic equivalence [14, 15], i.e., both sides have the same set of satisfying signals.
In this sense, we aim to decompose the overall synthesis problem into several subproblems with shorter horizons and fewer specifications, inspiring the modularized synthesis of the original specification. More precisely, we focus on the following fragment of complex formulas,
(5) |
where , , and are the safety, progress, and target subformulas, for and , , , , and are the boolean formulas that only contain predicates connected with logical operators , , and , and , , and are the non-empty syntactic intervals of the subformulas. We also refer to , , and which represent the complete coverage of the subformulas as their complete intervals, making a clear distinguishment with the syntactic intervals.
Similar to the popularly used GR(1) specifications [20], the fragment defined above is a complex STL formula composed of three components representing meaningful specifications for practical tasks. The safety part consists of a series of always subformulas specifying the conditions that should always hold. This could include for example safety rules applicable to the system. The progress component contains the always subformulas with eventual operators embedded to represent the tasks that should be performed regularly, such as the monitoring routines. The target component describes the task that should be achieved within a strict deadline. An always formula is embedded to ensure the holding of the target condition for a minimum time.
Specifications in the form of eq. (5) already have a natural division in subformulas for individual subtasks. However, modularized synthesis also requires the division of the subformulas in time. Given a set of ordered timing points , , , , we intend to split the specification into subformulas with shorter lengths. Then, modularized synthesis expects to efficiently solve the synthesis problem for through a sequence of synthesis problems for its subformulas . To achieve this, the overlapping between the timing intervals of the subformulas should be eliminated to decouple the dependence of different timings. In the next section, we will show that the decoupling of the safety subformulas can be achieved by syntactic separation while ensuring the syntactic equivalence between the separated specification and the original one. However, the progress and the target subformulas are challenging to decouple since the timing overlapping cannot be eliminated by merely using syntactic separation. This has not been well investigated by existing work. We will also show that these subformulas can be decoupled using the complete specification split which ensures soundness but introduces conservativeness. Our work is the first to decompose such STL formulas for modularized synthesis in the literature.
III Main Results
In this section, we will first show how to split the syntactic intervals of a complex specification while ensuring the syntactic equivalence. Then, we further present a complete split form to eliminate the overlapping of the complete intervals of the subformulas while causing certain conservativeness. Finally, we give the modularized synthesis algorithm based on these separation forms.
III-A Syntactic Timing Separation
The syntactic separation form of a complex specification in eq. (5) is defined as follows.
Definition 1 (Syntactic Timing Separation)
Given an ordered sequence of timing , , for , , the specification defined in eq. (5) is said to be in a syntactic timing separation form if
(6) |
where, for each ,
and all intervals associated to satisfy , , , , and , where are the numbers of the effective safety and progress subformulas for . ∎
Consider the following specifications with the same length : , , , and , where , are boolean formulas. Consider splitting points , , , according to Definition 1, only and are in a form that is syntactically separated by , , . Formulas , are not since splits the intervals .
We are interested in translating the specification (5) into the separated form of (6) using syntactic separation. In this way, the individual numbers of the safety and progress specifications for each timing interval , denoted as , , can be substantially smaller than those of the corresponding safety and progress specifications, i.e., , . The following syntactic separation principles can be used to transform (5) into (6) with syntactic equivalence guaranteed.
Lemma 1 ([14])
The following properties hold for arbitrary STL formulas , , and , with , : , , , . ∎
Lemma 2
The following conditions hold for arbitrary STL formulas , , and defined in Sec. II-A.
1). , for any , where both sides are true for signal , if and only if .
2). holds for any .
3). For any , , and hold for , . ∎
Lemma 3
Given , and an arbitrary STL formula , and hold. ∎
Theorem 1 (Arbitrary Syntactic Separation)
Given , the following conditions hold for an STL formula ,
(7) |
with . Moreover, the following conditions hold,
(8) |
for , , , , . ∎
Lemmas 2 and 3 provide complementary properties to previous work on syntactic separation [14, 15]. Note that they apply to all STL formulas as introduced in Sec. II-A, but not only the fragment in eq. (5). Most important is theorem 1 which allows separating a subformula into the logical combination of shorter subformulas with an arbitrary number of timing points. Such separation as eq. (6) does not change the syntax of the specification. i.e., for any signal with , . Nevertheless, syntactic timing separation only splits up the syntactic interval of a subformula, which does not eliminate the overlapping between the complete intervals of the subformulas. This is not sufficient for the modularized synthesis of specifications. In the following, we will give an alternative sufficient form of separation that is no longer equivalent to the original specification but ensures the separation of the complete intervals of the subformulas. This form is more conservative than the original specification but ensures the soundness of the solution and allows for modularized solutions to the synthesis problem.
III-B Complete Specification Split for Modularized Checking
Before we give the complete splitting form of specification (5), we first explain why eliminating the overlapping of the complete intervals of subformulas is important to modularized model checking which is the foundation of modularized synthesis to be explained in the following. Consider an STL specification and a signal prefix with the same length. For a given series of timing points , modularized model checking investigates under what conditions and what subformulas , , , , where for all , it ensures that
(9) |
In such a way, we can split the model checking of the original signal and specification into -steps of model checking for shorter signals and specifications . This is only feasible when the coverage or the complete interval of the subformulas is confined within the corresponding interval such that it does not overlap with those of other subformulas. Otherwise, the model checking for the left side of (9) can not be performed independently for each due to the coupled timing dependence.
Based on this consideration, we give the complete specification split form for formula in eq. (5) as
(10) |
where, for any ,
where for any , is the number of such that , i.e., the number of progress formulas that exceed the interval , and for any , is a heuristic value to be determined beforehand. It can be verified that . Then, we have the following two theorems to address the relation between the complete split form in eq. (10) and the syntactic separation form in eq. (6).
Lemma 4 (Complete Interval Split)
Given , , , and a specification in form (10), if for all and for all , the complete intervals of , , , do not overlap, and the complete intervals , , , do not overlap.
Lemma 5 (Soundness)
Theorem 2
Theorem 2 has solved the main problem of modularized model checking for specification given in eq. (5) by eliminating the overlapping between the complete intervals of its subformulas, as addressed by lemma 4. From a practical perspective, the overlapping means that the timing coupling between different subtasks specifies that these subtasks need to be executed in parallel. In this sense, theorems (2) provide a solution to decouple such dependence by imposing additional specifications to the subtasks, such that they can be solved independently in sequence. The soundness of the complete interval split is ensured by lemma 5. The timing points that mark the solving sequence can be predetermined according to practical requirements.
III-C Modularized Synthesis of Split Specifications
Given the complete specification split form in eq. (10) for modularized model checking, we can further investigate the modularized synthesis by incorporating the constraints brought up by the dynamic systems (2). For this, we develop algorithm 1 for modularized synthesis of a split specification. In algorithm 1, opt() is a function of the optimization problem in eq. (3) with interface , and FEASIBLE is a binary variable to indicate whether problem (3) is feasible. Algorithm 1 allows us to perform synthesis for the dynamic system (2) with specification in a modularized way, i.e., by solving a sequence of smaller synthesis problems in a timing order , , , . For each time , , the synthesis subproblem requires substantially fewer integers than the original problem since it involves much shorter and fewer specifications.
Complexity Analysis: As addressed in Sec. II-C, the complexity of directly synthesizing the original specification in eq. 5 is , where is the length of and is the total number of subformulas. For its complete split form in eq. (10), assume that the longest subformula has a length , the complexity of algorithm 1 is , where denotes the maximum number of subformulas in one synthesis module . As addressed in Sec. III-A and Sec. III-B, from syntactic separation we can expect and for any , which leads to . Moreover, we can also ensure by properly selecting the timing points , , , . Thus, with , modularized synthesis can substantially reduce the complexity of the synthesis problem for long and complex specifications and improve its efficiency.
Limitations: Nevertheless, a limitation of algorithm 1 is that it only ensures soundness but not optimality nor completeness to the original problem. This means that if it generates a feasible solution , it is certainly a feasible solution to the synthesis problem of the original specification, i.e., (soundness). However, it might not be the optimal solution in terms of the robustness , i.e., local optimality does not necessarily lead to global optimality. Moreover, if algorithm 1 is not feasible, it does not mean that the original synthesis problem is also infeasible (completeness). However, this is already sufficient for most practical robotic tasks. It is also worth noting that algorithm 1 might not be feasible for an arbitrary initial system condition . For a system (3) and a specification in eq. (10), the initial condition that ensures the feasibility of belongs to a set which is referred to as the largest satisfaction region [21]. How to utilize the feasible sets to improve the feasibility of a synthesis problem is also partially discussed in a recent work [16]. We are not providing further discussions on this since it is out of the scope of this paper.
IV Case Study in Simulation
In this section, we use an essential simulation study to showcase how the proposed modularized synthesis approach can be used to efficiently solve a synthesis problem for a complex specification. As shown in Fig. 1, we consider a scenario where a mobile robot is required to perform a monitoring task in a rectangular space SAFETY sized (red) with three square regions TARGET (yellow), HOME (green), and CHANGER (blue) which are centered at , , and with the same side length . The robot is described as the following dynamic model,
(11) |
where denotes the planar coordinate of the robot position at time step and is the position increments of the robot per step as the control input of the system. The control input of the system is subject to saturation constraints , for all , where are the elements of . The monitoring task is described as follows.
1). Starting from position , the robot should frequently visit TARGET every steps or fewer until .
2). From to , once the robot leaves HOME, it should get back to HOME within time steps.
3). After and before , it should stay in CHANGER continuously for at least time steps to charge.
4). The robot should always stay in the SAFETY region.

These tasks can be specified using the following formulas: , , , and respectively, where , , , and are boolean formulas used to specify TARGET, HOME, CHARGER, and SAFETY, for . Thus, the overall robot task is the conjunction of these formulas. With splitting timing points , , , and , the overall specification can be represented as a syntactic separation form as eq. (6), i.e., , where , , , , , .
We transform the overal specification into a complete split form as eq. (10), i.e., , where , , , , , , where the heuristic values are all determined as . Then, we use Algorithm 1 to solve an open-loop control signal for system (11) with the split specification . The stlpy toolbox [7] is used to implement the opt() method in algorithm 1. The program for this simulation study is published at [22]. The resulting robot trajectory is shown in Fig. 1 and Fig. 2. The trajectories in different stages are marked with different colors.

From Fig. 1 and Fig. 2, it can be seen that the robot starts from the initial position , reaches the TARGET at and stays there until . From , the robot oscillates between TARGET and HOME to satisfy the task requirements 1) and 2). After , the robot maintains the visiting frequency to HOME, while taking time to charge itself, which satisfies condition 3). During the entire process, the robot is restricted within the SAFE region, which satisfies specification 4). Therefore, all task specifications are satisfied, which indicates the efficacy of the proposed timing separation approaches and modularized synthesis methods.
V CONCLUSIONS
In this paper, we discuss how to split a big synthesis problem for a complex and long STL specification into several smaller optimization problems with less complexity. The two proposed separation forms for the specification, namely a syntactically separated form and a complete splitting form, allow us to solve these smaller problems in a modularized manner, which is an important step toward efficient optimization-based specification synthesis. There are still two limitations of our work. One is that we only investigate the modularized synthesis for a certain class of STL formulas, although it is sufficient for many practical tasks. The other one is that the feasibility condition of modularized synthesis has not been deeply studied. Our future work will extend the results to wider fragments of STL formulas. We will also incorporate the feasible sets of specifications to investigate the feasibility of modularized synthesis.
APPENDIX
V-A Proof of Lemma 2
For 1), from the definition of STL syntax, we know, for an arbitrary STL formula , indicates that there must exist , such that , which means . Then, from and lemma 1, we know .
V-B Proof of Lemma 3
V-C Proof of Theorem 1
V-D Proof of Lemma 4
For any , we know for all and for all . Thus, given and , the complete interval of reads , since in eq. (10) is already in a syntactic separation form. Thus, we know that the complete intervals of for all do not overlap. Then, for the complete interval of , we have , which implies that the complete intervals of for all do not overlap.
V-E Proof of Lemma 5
It can be noticed that and share the same safety formulas and also the same progress formulas with , for , for all . Thus, these subformulas already have split complete intervals and ensure the same semantics between and . Thus, we directly look into the progress formulas with for which we have using theorem 1. Note that means that, there should always exist and , such that and . In this sense, it is straightforward to infer that, for any , we have . Therefore, we have .
Now, looking into the target subformulas, it is easy to verify that holds for all , which leads to . Then, we can summarize that which leads to .
V-F Proof of Theorem 2
We first look into condition 1). For , it addresses . Also, according to the semantics of STL formulas, for any , where is an STL formula, for , if and the complete intervals of and do not overlap, we have . Applying this recursively from back to , we obtain , i.e., . This inference indicates 1). Note that this only holds if the complete intervals of , , , do not overlap, which is ensured by lemma 4.
For condition 2), if there exists , such that , we know that there exists , such that which implies since for all . This renders 2). Therefore, we can summarize that 1) 2) . Considering lemma 5, we further have 1) 2) .
References
- [1] E. Plaku and S. Karaman, “Motion planning with temporal-logic specifications: Progress and challenges,” AI communications, vol. 29, no. 1, pp. 151–162, 2016.
- [2] X. Li, G. Rosman, I. Gilitschenski, C.-I. Vasile, J. A. DeCastro, S. Karaman, and D. Rus, “Vehicle trajectory prediction using generative adversarial network with temporal logic syntax tree features,” IEEE Robotics and Automation Letters, vol. 6, no. 2, pp. 3459–3466, 2021.
- [3] V. Raman, A. Donzé, M. Maasoumy, R. M. Murray, A. Sangiovanni-Vincentelli, and S. A. Seshia, “Model predictive control with signal temporal logic specifications,” in 53rd IEEE Conference on Decision and Control. IEEE, 2014, pp. 81–87.
- [4] V. Kurtz and H. Lin, “A more scalable mixed-integer encoding for metric temporal logic,” IEEE Control Systems Letters, vol. 6, pp. 1718–1723, 2021.
- [5] L. Lindemann, G. J. Pappas, and D. V. Dimarogonas, “Reactive and risk-aware control for signal temporal logic,” IEEE Transactions on Automatic Control, vol. 67, no. 10, pp. 5262–5277, 2021.
- [6] A. Salamati, S. Soudjani, and M. Zamani, “Data-driven verification of stochastic linear systems with signal temporal logic constraints,” Automatica, vol. 131, p. 109781, 2021.
- [7] V. Kurtz and H. Lin, “Mixed-integer programming for signal temporal logic with fewer binary variables,” IEEE Control Systems Letters, vol. 6, pp. 2635–2640, 2022.
- [8] M. Srinivasan and S. Coogan, “Control of mobile robots using barrier functions under temporal logic specifications,” IEEE Transactions on Robotics, vol. 37, no. 2, pp. 363–374, 2020.
- [9] L. Lindemann and D. V. Dimarogonas, “Control barrier functions for signal temporal logic tasks,” IEEE control systems letters, vol. 3, no. 1, pp. 96–101, 2018.
- [10] D. Gundana and H. Kress-Gazit, “Event-based signal temporal logic synthesis for single and multi-robot tasks,” IEEE Robotics and Automation Letters, vol. 6, no. 2, pp. 3687–3694, 2021.
- [11] S. Liu, A. Saoud, P. Jagtap, D. V. Dimarogonas, and M. Zamani, “Compositional synthesis of signal temporal logic tasks via assume-guarantee contracts,” in 2022 IEEE 61st Conference on Decision and Control (CDC). IEEE, 2022, pp. 2184–2189.
- [12] S. Alatartsev, S. Stellmacher, and F. Ortmeier, “Robotic task sequencing problem: A survey,” Journal of intelligent & robotic systems, vol. 80, pp. 279–298, 2015.
- [13] T. Wongpiromsarn, U. Topcu, and R. M. Murray, “Receding horizon temporal logic planning,” IEEE Transactions on Automatic Control, vol. 57, no. 11, pp. 2817–2830, 2012.
- [14] P. Hunter, J. Ouaknine, and J. Worrell, “Expressive completeness for metric temporal logic,” in 2013 28th Annual ACM/IEEE Symposium on Logic in Computer Science. IEEE, 2013, pp. 349–357.
- [15] K. Bae and J. Lee, “Bounded model checking of signal temporal logic properties using syntactic separation,” Proceedings of the ACM on Programming Languages, vol. 3, no. POPL, pp. 1–30, 2019.
- [16] X. Yu, C. Wang, D. Yuan, S. Li, and X. Yin, “Model predictive control for signal temporal logic specifications with time interval decomposition,” arXiv preprint arXiv:2211.08031, 2022.
- [17] O. Maler and D. Nickovic, “Monitoring temporal properties of continuous signals,” in Formal Techniques, Modelling and Analysis of Timed and Fault-Tolerant Systems: Joint International Conferences on Formal Modeling and Analysis of Timed Systmes, FORMATS 2004, and Formal Techniques in Real-Time and Fault-Tolerant Systems, FTRTFT 2004, Grenoble, France, September 22-24, 2004. Proceedings. Springer, 2004, pp. 152–166.
- [18] L. Nenzi and L. Bortolussi, “Specifying and monitoring properties of stochastic spatio-temporal systems in signal temporal logic,” EAI Endorsed Transactions on Cloud Systems, vol. 1, no. 4, 2015.
- [19] G. E. Fainekos and G. J. Pappas, “Robustness of temporal logic specifications for continuous-time signals,” Theoretical Computer Science, vol. 410, no. 42, pp. 4262–4291, 2009.
- [20] M. Schlaipfer, G. Hofferek, and R. Bloem, “Generalized reactivity (1) synthesis without a monolithic strategy,” in Haifa Verification Conference. Springer, 2011, pp. 20–34.
- [21] C. Belta, B. Yordanov, E. Aydin Gol, C. Belta, B. Yordanov, and E. Aydin Gol, “Largest satisfying region,” Formal Methods for Discrete-Time Dynamical Systems, pp. 119–139, 2017.
- [22] Z. Zhang and H. Sofie, “Benchmark for modularized synthesis of complex specifications,” GitHub repository, 2023. [Online]. Available: https://github.com/zhang-zengjie/modustl