Investigating impact of bit-flip errors in control electronics on quantum computation

Quantum circuits are crucial for manipulating information in quantum computing. These circuits consist of quantum gates arranged in a sequence to perform complex computations through the coherent manipulation of qubits. In a typical superconducting quantum computer, quantum gates correspond to microwave pulses that act upon qubits.

A comprehensive depiction of a qubit control system is presented in Fig. 1 integrating both the architectural and operational aspects of FPGA-based RF control systems used in quantum computing. This system, built on advanced FPGA technology, provides a robust platform for qubit pulse generation and quantum state measurement, enabling fully parametric waveform generation that offers complete control over all operational layers (Xu et al., 2021). It integrates room temperature electronics hardware, FPGA gateware (i.e., the module consisting of ADC, DAC and FPGA), and engineering software to accurately generate and measure RF pulses for qubit control. Furthermore, this system serves as a platform for developing and refining real-time feedback control strategies, such as rapid reset (Vijay et al., 2012; Ristè et al., 2012). The hardware utilizes the heterodyne method for compact RF signal generation and detection. It comprises three primary modules: an FPGA/ADC/DAC module for producing and detecting the intermediate frequency (IF) signal, an RF mixing module to shift the signal frequency to or from the desired frequency, and a local oscillator (LO) generation module that delivers low-noise LO signals essential for accurate qubit manipulation.

The process of implementing a quantum circuit using a Quantum Processing Unit (QPU) begins with the user specifying the desired quantum circuit, as illustrated in Fig. 1. The user submits the specifications of the desired quantum circuit to a cloud interface, where it undergoes preliminary processing and optimization for hardware compatibility. The refined instructions are then relayed to the FPGA, the central controller, which directly manages the quantum hardware operations. Inside the FPGA, the instruction cycle commences with the retrieval of the corresponding pulse for each specified quantum gate from the FPGA’s memory. This memory is meticulously organized to store detailed amplitude and phase information essential for generating the precise pulse for each gate operation. Specifically, if the quantum system is designed to handle five qubits and is capable of implementing five different gates, the FPGA’s memory will contain a dataset of 25 unique pulses, effectively covering every possible combination of qubit and gate. Once the appropriate pulse data is identified, it is extracted from the memory. This data includes specific values for amplitude and phase that are crucial for the accurate execution of the quantum gates. Following retrieval, this pulse information is processed through the DAC, which converts the digital pulse data into an analog signal. This signal is then modulated and amplified to ensure it meets the exact requirements for interacting with the qubits. The final output from the modulator, now an RF pulse, is fed into the QPU. Concurrently, the ADC monitors the outputs from the QPU, capturing the results of quantum operations. These results are then processed by the FPGA and sent back through the cloud interface to the user, providing data for real-time adjustments and further analysis.

In quantum computing, where precise control is paramount, FPGAs leverage Block RAM (BRAM) for tasks like storing pulse envelopes used in qubit gate calibration. BRAM is particularly well-suited to this role due to its ability to efficiently store real and imaginary parts of the complex numbers and facilitate rapid, frequent access to these data blocks, crucial for maintaining high-speed operations. It offers significant advantages including the efficient organization and retrieval of complex data, notably the in-phase and quadrature-phase components of control pulses. Moreover, BRAM’s fast access speeds outperform those of distributed or external memory solutions, crucial for operations where timing and synchronization are critical. Additionally, its flexibility to be dynamically configured for various data types and its capability for efficient repeated access to stored data allow FPGAs to quickly adapt and reuse pulse envelopes, even as operational parameters like carrier frequency or phase vary. This makes BRAM an invaluable resource in the architecture of quantum computing systems, enhancing both performance and efficiency.

FPGAs, being classical devices, are susceptible to bit-flip errors. Bit flip errors in the BRAMs of an FPGA can occur due to several factors, often related to the physical and environmental conditions in which the FPGA operates such as radiation effects, electrical noise, and temperature variations (Salami et al., 2018; Rakin et al., 2021; Rollins et al., 2010). The BRAMs in FPGAs used in quantum computer control electronics undergo further challenges like intense operations to meet the high performance requirements which can create additional noise in the system (e.g., power supply droop). This, in turn, can cause read/write/retention failures. Such intense operations and subsequent errors can also be adversary induced. For example, adversary sharing the same quantum hardware as victim in multi-tenant computing environment can write a Trojan program to generate frequent pulses increasing power consumption and subsequent supply noise. An insider adversary can also consider non-invasive tampering of the FPGA to inject bit flip errors by manipulating ambient conditions. The impact of bit flip errors in BRAMs can be significant due to the precision and sensitivity required in quantum computing. Some specific reasons that could lead to bit flip errors or similar memory disturbances in quantum computer control electronics are tabulated in Table 1. To make the matter worse, current state-of-the-art FPGAs do not support ECC (Error Correcting Code) on BRAMs by default. For example, single port BRAM in Xilinx FPGAs are not ECC protected (Xilinx, 2020).

Bit flip errors in FPGA memory can disrupt quantum operations by causing faulty pulse generation. Fig. 2 illustrates the pulse shape of a Hadamard Gate from IBM’s FakeValencia Backend obtained using Qiskit. The bottom part of the figure shows the actual pulse shape, with the amplitude represented as a 32-bit floating-point number stored in the FPGA memory. If a bit flip occurs, such as a flip in the third bit, the amplitude undergoes a dramatic decrease from its original value of 0.09618851775276127+0.0008448724348311288j to a bit-flipped value of 2.239563395844968e-11+0.0008448724348311288j. This significant reduction (also shown in Fig. 2) can lead to substantial errors in the quantum computing outcomes.

This paper provides a comprehensive analysis of the effects of bit flip errors in FPGA memory, specifically within the context of quantum computing control systems. We have conducted a series of controlled sensitivity analysis where single bits in the amplitude (both real and imaginary components) and phase values of quantum pulses were flipped. These experiments were carried out using various IBM quantum fake backends, which simulate real quantum computing environments. This approach allows for a precise understanding of how such errors affect quantum gate operations. Secondly, our analysis goes beyond general fault impacts by examining the specific effects of bit flips on the functionality and performance of various native quantum gates such as Hadamard, NOT, and Rotation-gates. Finally, we propose repetition code to protect the important bits of the BRAM and mitigate the impact of bit-flip errors.

In the remainder of this paper, Section 2 provides a background on the role of FPGAs in quantum control systems and explains the basics of quantum pulse specification and data representation. Section 3 details our experimental setup and findings on the bit flip errors. Section 4 presents the analysis with 3-bit repetition code to mitigate the impact of bit flip errors. Finally, Section 5 draws conclusions.

FPGAs are integral to the architecture of modern quantum control systems due to their versatility, reconfigurability and performance. Qubits exhibit quantum mechanical properties that is harnessed in quantum computing to perform complex calculations more efficiently than classical computers. The role of FPGAs in these systems is multifaceted. They generate precise and high-frequency signals needed to manipulate qubits through quantum gates. This manipulation is critical for executing quantum algorithms. FPGAs can dynamically adjust these signals in response to real-time feedback from the quantum system, which is crucial for maintaining the delicate state of qubits during computations. Moreover, the reconfigurability of FPGAs offers a significant advantage. As quantum algorithms evolve and new quantum error correction codes are developed, the underlying hardware must also adapt. FPGAs allow for these rapid changes without the need for replacing physical components, unlike application-specific integrated circuits (ASICs) which are hard-coded to perform specific tasks. FPGAs also contribute to error management in quantum systems. They process readout signals from qubits to detect and correct errors on the fly. This capability is vital for quantum error correction, which is essential to counteract the inherent instability of qubits and ensure the accuracy of quantum computations.

The integration of FPGAs into quantum computing extends beyond mere functionality. They enhance the scalability of quantum computers. As systems expand to include more qubits, the complexity of control tasks increases exponentially. FPGAs handle this scalability efficiently, managing multiple tasks simultaneously and sustaining the synchronization required for complex quantum operations.

We utilized the Qiskit framework to simulate quantum circuits and manipulate quantum pulse sequences on IBM’s fake quantum backends, specifically FakeValencia, FakeManila and FakeLima. These environments allow for the realistic simulation of quantum computational processes without the need for actual quantum hardware.

Our experimental investigation began with a systematic study of bit flip errors across multiple fake backends provided by IBM: FakeValencia, FakeManila, and FakeLima. We focused on manipulating the real part of the amplitude of the pulse envelope for quantum gates pulses, specifically the X and H gates, which are fundamental to a wide array of quantum algorithms. For each gate, we flipped each of the 32 bits one at a time in the real component of the amplitude and observed the outcomes. It should be noted that during our experiments, specific exponent bits, notably bit 1 and bit 6, resulted in invalid pulses because the maximum pulse amplitude norm exceeded 1.0. We assume that such extreme conditions would be immediately recognized by the system’s error detection protocols to halt the transmission of the pulse. In our experiments, to provide an uninterrupted visual trend, we employed a linear interpolation method to estimate the missing TVD values by connecting the adjacent data points directly.

Interestingly, the trends observed in the impact of bit flips were consistent across the three backends. This uniformity was evident in both the X and H gates, as illustrated in Fig. 3 (a) and (b), respectively. TVD increase measurements showed similar patterns of sensitivity and resilience to specific bit flips, regardless of the backend.

For TVD increase calculations, firstly, we compute the TVD between the outcomes from the bit-flipped pulse settings and the ideal theoretical outcomes, which we refer to as ‘TVD flipped vs. ideal’. Secondly, we compare the original, unmodified pulse settings against the ideal outcomes, termed ‘TVD original vs. ideal’. The TVD increase is then quantified as the difference between these two values, effectively measuring the additional deviation caused by flipping a bit in the pulse’s amplitude. Notably, flipping the first bit, which is the sign bit, did not show a significant impact on the TVD. This indicates that the changes in the sign of the pulse’s amplitude have a minimal effect on the operational characteristics of the gate. Further, detailed observation of bits 1 to 8, which represent the exponent part of the floating-point representation, revealed a consistently high TVD increase. Flipping any of these bits causes substantial changes in the amplitude’s magnitude, leading to dramatic shifts in quantum gate behavior. Specifically, bits 9 to 17 within the mantissa also showed significant TVD increases, suggesting these higher-order bits play a crucial role in defining the precision of the pulse amplitude. In contrast, bits 18 to 31, which represent the lower-order part of the mantissa, exhibited a lesser impact on TVD, indicating their relatively minor role in affecting the quantum gate operations across the tested backends. This uniformity in response to bit flips was evident in both the X and H gates, as illustrated in Fig. 3 (a) and (b), respectively. TVD measurements showed similar patterns of sensitivity and resilience to specific bit flips, regardless of the backend.

The consistency in the experimental results across different backends can be attributed to the standardized simulation protocols used in Qiskit, which are designed to mimic the physical behaviors of actual quantum devices. These protocols ensure that the fundamental physics governing quantum operations are uniformly modeled, regardless of the specific backend. Therefore, the effects of modifying bit values in the amplitude’s real part are similarly reflected across all simulated environments. Given the similar trends observed and to streamline our experimental process, we chose to continue detailed experiments solely on FakeValencia. This approach allows for more efficient use of resources and simplifies our analysis without sacrificing the breadth of applicability of our results. The choice of FakeValencia, while arbitrary among the three, provides a representative sample that is likely indicative of general behaviors in other simulated quantum computing environments.

We extended our experiments to include additional quantum gates such as the SX, CNOT, and rotation gate, Rx at $\pi/4$ and $\pi/3$ angles. These experiments focused on how bit flips in the real part of the pulse amplitude affect the functionality of these gates, as shown in Fig 4. We note that the exponent bits (bits 1-8) of the floating-point representation have a significant impact on the amplitude, greatly affecting gate operations when altered. For example, flipping just one exponent bit in the X gate led to a nearly 200% increase in TVD. This happens because the exponent bits scale the amplitude exponentially, leading to large changes in the pulse’s magnitude. Such changes can result in incorrect quantum operations, highlighting the importance of these bits for the accuracy of quantum gates. The SX and H gates also show a strong sensitivity to changes in the exponent bits, but to a lesser extent than the X gate.

In contrast, the Rx and CNOT gates demonstrated more resilience to these bit flips. This resilience could be due to the specific roles these gates play in quantum circuits. The Rx gates, which perform rotations around the x-axis by specific angles, might be less affected by small amplitude changes because their primary function is to change the phase of the qubits rather than their state. As for the CNOT gate, its operation as a two-qubit control gate might inherently buffer it against the impact of amplitude changes in single-qubit control lines. Its functionality relies more on the relative states of two qubits rather than on the precise amplitude of a control pulse.

Additionally, bit flips beyond bit 17 showed minimal effect across all gates tested. This is consistent with the nature of the mantissa in floating-point numbers, where the lower-order bits influence only the precision of the pulse amplitude. These details have limited impact on the quantum gates’ operational characteristics, demonstrating the gates’ ability to perform correctly despite minor perturbations.

We also analyzed the effects of bit flips in the imaginary part of the pulse amplitude across various gates, except the X gate which does not utilize an imaginary component in its amplitude. From Fig. 5, it is clear that the Total Variation Distance (TVD) increase shows no consistent pattern or trend across the different bit positions, whether they are in the exponent or the mantissa. This diminished sensitivity can be attributed to the relatively smaller magnitude of the imaginary part of the pulse amplitude compared to its real counterpart. For example, the amplitude for the H gate on FakeValencia backend is recorded as 0.09618851775276127+0.0008448724348311288j, where the imaginary part is much smaller than the real part. Therefore, alterations to the imaginary component through bit flipping have a reduced effect on the gate’s functionality due to its lower numerical influence.

Additionally, similar to bit flips in the real part, the Rx and CNOT gates demonstrate greater resilience to errors in the imaginary part. This resilience could stem from the structural and operational characteristics of these gates. The Rx gates, designed to perform precise rotational operations, and the CNOT gate, functioning as a two-qubit control gate, may inherently possess robust error handling mechanisms that mitigate the impact of slight amplitude variations, particularly those affecting the less significant imaginary part.

In the next experiment, we analyzed the impact of bit flips on the phase shift values of quantum gates utilizing the ShiftPhase instruction. The results, shown in Fig. 6, revealed that bit flips in phase shift values do not follow a consistent pattern across different bits, either in the exponent or mantissa. This observation suggests a uniform sensitivity to phase errors across the binary representation of the phase values, which is crucial for understanding the robustness of quantum gates against such errors. The TVD impacts were generally lower compared to those from amplitude bit flips, indicating a milder impact on quantum operations. This reduced sensitivity can be understood in terms of the specific role of the ShiftPhase instruction, which is critical as it updates the modulation phase of subsequent pulses on the same channel. This instruction does not alter the pulse amplitude but adjusts the phase angle $\phi$ of the output signal, impacting all following pulses. Such phase adjustments are essential for the precise control required in quantum operations, and the fact that they do not directly change the amplitude means that errors in phase values may have a less disruptive impact on the overall quantum state compared to amplitude errors. Gates such as the Rx and CNOT showed greater resilience to these phase errors, likely due to their inherent error handling capabilities within their operational structures.

In our study of bit flip effects on the real part amplitude of quantum gate pulses, the most significant impacts were observed in the exponent bits (bits 1-8) and the first nine bits of the mantissa (bits 9-17), as indicated by the darker shading in Fig 7. Conversely, bits beyond the 17th position and the sign bit showed minimal effect on operational outcomes, marked by lighter shading in the figure. Given that bits 1 and 6 of the exponent consistently resulted in invalid pulses when flipped exceeding the maximum allowable pulse amplitude, we assume the system will detect these errors and halt operations. This assumption allows us to strategically exclude these bits from our error correction efforts. We can then focus on safeguarding the remaining impactful bits (2-5, 7-17).

We propose employing a 3-bit repetition code specifically for the seven bits that most significantly affect quantum gate operations: bits 2, 3, 4, 5, 7, 8, and 9. This error-correcting strategy involves encoding each of these critical bits into three bits. For example, if a bit originally has a value of ‘1’, it will be encoded as ‘111’; similarly, a ‘0’ would be encoded as ‘000’. This tripling of each bit enhances the system’s ability to detect and correct single bit errors by allowing a majority vote among the three bits to determine the correct value. In majority voting, the most common value among the three replicated bits is chosen as the correct value. For instance, if the received triplet is ‘010’, the system recognizes that an error has occurred and corrects it to ‘000’ based on the majority of bits being ‘0’.

To implement error correction without increasing the overall memory overhead, we repurpose fourteen less critical bits (specifically, bits 18-31) to encode each of the seven high-impact bits (bits 2, 3, 4, 5, 7, 8, and 9) into three bits. This reallocation effectively utilizes the memory space that would otherwise hold less crucial data. The bits in positions 10-17, while still impactful, will not be encoded due to memory constraints, balancing the need for error correction with the available memory resources.

The effectiveness of this coding scheme is described using the $[n,k,\delta]$ notation, where $n$ is the number of bits in the encoded word, $k$ is the number of original data bits, and $\delta$ is the Hamming distance of the code. For the 3-bit repetition code used here, the parameters are as follows: $n=3$ indicates that each bit is expanded to three bits, $k=1$ shows that each triplet originates from one original bit, and $\delta=3$ represents the Hamming distance. The Hamming distance of three means that the code can detect up to two errors and correct one error within each triplet of bits.

The results, shown in Fig. 8, indicate that TVD significantly decreased for bits 2, 3, 4, 5, 7, 8, 9 after error correction (e.g., below 7% compared to $\sim$ 200% before correction). When a bit flip is detected within these encoded triplets, the majority voting process corrects it, effectively restoring the original bit value. However, it is important to note that the TVD did not drop to zero for the error-corrected bits. This can be attributed to the loss of some information due to our strategy of discarding the less impactful bits (18 to 31) to make room for encoding the more critical bits. This trade-off was necessary to balance error correction with memory constraints. For the bits between 10 and 17, which we could not encode due to memory constraints, the TVD was higher compared to the error-corrected bits but still remained under 40%. This observation highlights that even without applying error correction to all bits, our system still demonstrates strong resilience. Note that implementing the 3-bit repetition code for 7 specific bits involves additional logic circuits to encode each bit into triplets and to handle the majority voting mechanism. These modifications require extra FPGA resources, which could affect the overall system efficiency and complexity. However, the benefits of improved error correction and system reliability often justify the minor added complexity in critical applications like quantum computing.

Finally, we conducted experiments to rigorously test the effectiveness of our error correction strategy under simulated real-world conditions. Over the course of 100 runs, we randomly flipped one bit at a time in the real part of the amplitude of the X gate. This methodology was crucial for evaluating how the system handles spontaneous errors that might occur during typical operations. The initial distribution of TVD increases, shown in Fig. 9 (red plot) before implementing the error correction, displayed a wide spread. Frequencies peaked sharply at $\sim$ 13%, indicating small change for some flips, and soared to nearly 200% for others, highlighting flips that caused severe disruptions in gate functionality. Upon applying the 3-bit repetition error correction method, the TVD distribution, as illustrated in Fig. 9 (green plot), narrowed markedly. Most increases were now tightly clustered around 3%, with no instances exceeding 35%. This significant reduction in TVD highlights the robust effectiveness of our error correction strategy.

One can use SECDED (Single Error Correction, Double Error Detection) (Hamming, 1950) instead of repetition code for better fault coverage at lower overhead. The number of parity bits ($k$) needed to protect 24 data bits (in our case) (($n$) can be calculated as follows:

The smallest $k$ that satisfies this condition for $n=24$ is 5, as $2^{5}-1=31$ meets the requirement $24+5=29$. Therefore, 5 parity bits can effectively manage 24 data bits. The 5 bits from the less impactful range of 24-31 can be repurposed to serve as these parity bits.

By analyzing the TVD data without error correction, we can estimate improvements in TVD after applying SECDED to the first 24 bits of quantum gate real amplitudes. This estimation assumes that the maximum TVD will occur for the remaining bits that are not corrected. For example, we project the TVD for the X gate to decrease to between 10% and 15%. Similar reductions are expected for other gates, with the H and SX gates likely seeing TVD decreases to around 20-25% and 15-20%, respectively, and the CNOT gate to between 15% and 20%. The rotation gates, Rx($\pi/4$) and Rx($\pi/3$), are anticipated to achieve even lower TVDs, ranging from 5% to 10% and 5% to 7%, respectively. These estimates also take into account the impact of discarding data from the 5 least impactful bits, which could contribute to residual TVD.