In-place Switch: Reprogramming based SLC Cache Design for Hybrid 3D SSDs

Figure 1 illustrates the architecture of a hybrid 3D SSD that integrates SLC and TLC spaces within a single storage device. The SSD architecture comprises two parts: 1) The front end consists of the control and communication units. The SSD controller handles read and write requests from the host interface and executes Flash Translation Layer (FTL) functions such as Address Mapping (AM), Garbage Collection (GC), and Wear Leveling (WL). The flash controller serves as the interface between the front end and the back end; 2) The back end consists of the data storage units that provide actual storage capacity. To boost SSD performance, the internal architecture employs four levels of parallelism: from channel to chip, die, and plane[12]. Each plane contains multiple blocks, which can only be written sequentially.

The primary distinction between 3D SSDs and 2D SSDs lies in the architecture of the flash block. As shown on the right of Figure 1, 3D SSDs employ a vertical block architecture. To transition from 2D to 3D, 3D SSDs introduce layers, with each layer consisting of multiple word lines on a horizontal plane, and each word line comprising multiple flash cells. TLC flash provides three types of bits for each cell, Least-Significant-Bit (LSB), Center-Significant-Bit (CSB), and Most-Significant-Bit (MSB). Traditionally, program operations shift the voltage state from ”erased” to a specific higher voltage level, representing three-bit values in TLC (LSB, CSB, MSB). Using three registers, one-shot programming enables the simultaneous writing of three pages to a single word line, a process known as ”one-shot programming” [10]. SSDs employ an out-of-place update strategy for program operations, where updates are written to free pages while the original pages are invalidated. A cell can only be reprogrammed after it has been erased.

Previous works [22, 4, 2, 3, 7, 29] have developed reprogram operations for both 2D and 3D flash memory. Reprogram operation refers to the process of reprogram flash cells that are at a certain voltage state to a higher voltage state before they are erased, thereby achieving in-place updates to reduce cell wear or improving the reading process. As shown in Figure 2, this process can accelerate reads in TLC SSDs [4]. The x-axis represents the voltage threshold, and the y-axis indicates the probability of each state. By charging flash memory cells with different amounts of electrons, the entire voltage range can be divided into eight states (E, P1$\sim$P7). If LSB bits are invalidated, the eight states of CSB and MSB bits can be grouped into four pairs (E-P7, P1-P6, P2-P5, P3-P4) due to identical data. Reprogramming the voltage thresholds in the first four states (E$\sim$P3) to the latter four states (P4$\sim$P7) can accelerate the read process [25].

However, two main challenges affect the reliability of reprogram operations: cell-to-cell interference [1] and background pattern dependency [17]. The former has a relatively minor impact, while the latter plays a more significant role in reducing reliability. Therefore, to maintain the reliability of flash memory, reprogram operations must be performed with caution. According to the verification of reprogram operation presented in [7], there are two restrictions for performing the technology: First, 3D TLC only can be randomly reprogrammed within two layers in 3D TLC SSDs without loss of reliability; Second, each TLC can be reprogrammed four times at most. In this work, these restrictions are strictly satisfied when reprogram operation is considered.

Modern commodity hybrid 3D SSDs combine SLC and TLC [5, 28], where SLC is used as the cache to store user data for boosting the performance of hybrid SSDs. As shown in the left part of Figure 1, during host writes, data is first written to the limited-capacity SLC cache. This approach leverages the higher performance of SLCs, resulting in improved overall SSD performance. Meanwhile, the TLC space ensures that the 3D SSDs maintain their high-density advantage, providing ample storage capacity despite the lower performance and reduced reliability compared to the SLC cache. When the SLC cache is full, the SSD controller performs GC, which involves migrating valid data and erasing used blocks to reclaim the SLC cache. Note that GC operations occur whenever SSD physical space is insufficient, not just when the SLC cache is full.

Since the SLC cache is engineered by only storing one bit in the original TLC, the size of the SLC cache should be carefully dimensioned. Allocating more TLC space to the SLC cache enhances performance but reduces overall capacity. Conversely, allocating less TLC space to the SLC cache preserves capacity but limits performance gains from the SLC cache. Traditionally, the SLC cache is allocated from a fixed portion of TLC space, preventing excessive consumption of TLC capacity. Typically, the size of the SLC cache in commodity SSDs ranges from several gigabytes (GBs) to over a hundred GBs [23, 9, 26]. For example, Samsung’s Turbo Write technology suggests that a 3GB SLC cache is sufficient for most daily use scenarios [26]. Other manufacturers, such as Micron, allocate larger SLC caches to accommodate data-intensive applications [23].

Previous works on hybrid SSDs can be categorized into several types: First, the size of the SLC cache is adjusted by considering the amount of data stored in the SSD or SSD’s status, thus better performance is achieved without significantly losing the capacity [30, 26, 23, 27]; Second, the SLC cache can be used to accelerate time-consuming activities, such as GC, so that the performance of SSDs is boosted [20, 31]; Third, the SLC cache is leveraged to store hot data, thus most GCs are triggered in SLC cache as it has better endurance and lower read and write latencies [13, 21, 19]; Fourth, to balance the wear rates of SLC and TLC, Jimenez et al. [14] proposes to distribute writes to the SLC cache or TLC space according to flash cells’ wear rate.

However, above mentioned works still need block reclamation to empty the SLC cache, which does harm to performance and lifetime of SSDs from the perspective of write latency and write amplification. Therefore, in this work, we attempt to alleviate block reclamation’s impact via reprogram operation.

IPS seeks to allocate a new SLC cache rather than reclaim the used SLC cache. To prevent excessive allocation of free TLC space, a new SLC cache is only allocated when the used SLC cache is fully reprogrammed, ensuring no capacity is wasted. Thus, in this design, if the SLC cache is full, host writes are utilized to reprogram SLC pages, converting them into TLC pages in place. This process not only continuously provides free SLC pages but also avoids additional data migration. Figure 6(b) illustrates the changes in voltage thresholds as SLC pages are reprogrammed into TLC pages. To construct the SLC cache, only two states are encoded in each TLC cell, storing one bit per cell. IPS initially programs the flash cells into the two lower voltage thresholds (compared to traditional SLC) to represent the two SLC states. If reprogram operation is needed to convert SLC back to TLC in place, the original data is first read and then rewritten with new data. Reprogramming the lower two voltage thresholds used for the SLC cache into the higher eight voltage thresholds required for TLC involves two reprogram operations.

However, considering the restrictions of reprogram operation [7], the SLC cache is allocated at the granularity of two layers per block. Initially, the first two layers of all blocks are allocated as SLC cache to provide basic SLC cache capacity. As shown in Figure 6(a), the first two layers (termed SLC layer) of all blocks in different planes (denoted as Plane 0 and Plane 1) are allocated and grouped as SLC cache. At the beginning, within each plane, all blocks containing the SLC layer are programmed sequentially to store data in SLC pages (Step 1). After all SLC layers in a plane have been exhausted, reprogram operations are performed in Step 2, requiring four operations to convert two SLC pages back to TLC pages. Once an SLC layer has been fully reprogrammed, the next two layers in the same block are allocated as new SLC layers. Consequently, subsequent writes can be processed at the SLC performance level again (Step 3).

For bursty access, IPS enhances performance over traditional SLC caches, as host writes benefit from the new SLC cache. For daily use, write amplification is reduced by substituting traditional idle-time data migration with reprogram operations, avoiding additional writes to the SSDs. However, reprogram operations are performed at the TLC performance level, leading to a decrease in performance. To address this, we propose leveraging advanced garbage collection techniques [15] to regain the high-performance benefits of the SLC cache while preserving the reduction in write amplification achieved by IPS.

Advanced GC (AGC) aims to divide GC into several atomic processes including multiple valid page migrations and erase operations. By moving these processes from runtime to idle time, AGC can hide its time cost and improve the performance of SSDs. In this work, IPS is designed with considering AGC (termed IPS/agc). IPS/agc leverages valid page migration of AGC to reprogram used SLC pages during idle time. In detail, instead of migrating data from the SLC cache to free TLC space, valid pages of AGC are read and reprogrammed to used SLC pages so that a new SLC layer can be allocated during idle time. IPS/agc can outperform traditional SLC cache due to three main reasons: First, no additional data migration occurs so that the write amplification IPS achieves can be maintained; Second, used SLC pages can be reprogrammed more frequently during idle time so that more new SLC cache can be allocated to store host writes in runtime; Third, valid page migration from AGC blocks can be flexibly interrupted to barely delay host writes.

Take Figure 7 as an example. Assume that the SLC cache is composed of two SLC pages. For a traditional SLC cache, if a host write arrives suddenly when block reclamation is being performed, it has to be delayed until the reclamation process is finished. Therefore, the conflict between host write and block reclamation can cause a large delay time. But for IPS/agc based SLC cache, to deal with the arriving write, valid page migration of AGC is interrupted in time, thus the arriving write can be directed to other SLC pages in the same plane with less delay time. Note that, reprogram latency is conservatively set to TLC program latency in this work.

To meet the demand for a large SLC cache capacity, we propose to cooperate IPS/agc cache with a traditional SLC cache. Due to the limitations of the reprogram operation, IPS/agc can only allocate a small portion of TLC space as an SLC cache. In the proposed cooperative design, the first two layers of the majority of blocks are designated as SLC layers within the IPS/agc cache. Subsequently, the remaining smaller portion of flash blocks is allocated as the traditional SLC cache.

In order to relieve performance cliffs and significant write amplification, the IPS/agc cache is prioritized for handling host writes, as shown in Figure 8. First, host writes are directed to the IPS/agc cache (Step 1). If no additional host writes arrive, valid page migration is performed within the AGC to reprogram the used SLC pages to TLC pages in the IPS/agc cache (Step 2.1). After which a new SLC layer is allocated within the IPS/agc. This cooperative design only activates the traditional SLC cache when sustained host writes require additional space, redirecting subsequent host writes to the traditional SLC cache (Step 2.2).

To ensure that subsequent writes can continuously benefit from the cooperative design, idle time is utilized not only to reprogram used SLC pages in the IPS/agc cache but also to reclaim the traditional SLC cache if it has been consumed. Since the data migration directions for the IPS/agc cache and the traditional SLC cache are opposite, data from the traditional SLC cache can be read and reprogrammed into the IPS/agc cache. This allows blocks in the traditional SLC cache to be reclaimed while used SLC pages in the IPS/agc cache are reprogrammed (Step 3.1). During this process, if all SLC pages in the IPS/agc cache have been reprogrammed but there are still blocks in the traditional SLC cache that have not yet been reclaimed, the data in these blocks are redirected to free TLC space (Step 3.2). After completing the data migration, the traditional SLC cache undergoes erase operations (step 4) to reclaim space. Conversely, if all data in the traditional SLC cache has been migrated but the IPS/agc cache still contains used SLC pages that have not been fully reprogrammed, valid page migration from the AGC will fill these gaps.

Thanks to most SLC cache technologies adopt dynamic SLC cache allocation, which determines the size of the SLC cache based on the amount of data stored in SSDs [23, 9]. Therefore, in this work, traditional SLC cache in cooperating design can be dynamically allocated without loss of generality.