Impact of Orientation on the Bias of SRAM-Based PUFs

The main component of an SRAM memory is the bitcell, which consists of two CMOS inverters interconnected in a positive feedback loop, forming a bistable storage element. The initial state of each bitcell is determined by the process variation that arises during the IC’s manufacturing. The stability of each bit is contingent upon the degree of threshold voltage mismatch between the local devices. The typical 6T-SRAM cell exhibits a preferred state due to stochastic variations in the threshold voltages of its transistors. This randomness in the initial values of 6T-SRAM results in a largely unpredictable, largely repeatable, and yet exclusive pattern of zeros and ones.

The architecture of the memory and different valid orientations are illustrated in Fig. 1. All SRAM memories are single-port and utilize 6 transistors per bitcell. Furthermore, we utilized two distinct types of memories. Those with a bitcell size of approximately $\sim$0.65$\mu m^{2}$ are labelled as low density and high speed, whereas those with a bitcell size of approximately $\sim$0.50$\mu m^{2}$ exhibit high density but low speed. The high-speed memory adopts Standard-vt for both periphery and bitcells, while the low-speed memory utilizes Mixed-vt for periphery and High-vt for bitcells.

SRAM macros can be internally arranged in a variety of ways. These are decisions that the memory compiler automatically performs given a user specification (i.e., desired number of addresses and datawidth). As shown in Fig. 1 (a), the memories generated by a commercial SRAM compiler have half of the bits on the right and the other half on the left. The control circuitry lies in the centre. This arrangement is identical for high-speed and high-density variants.

These large bitcell arrays are built by replicating a Memory matrix of size $m\times n$ repeatedly to form a larger matrix of size $M\times C$, as depicted in panel (b) of Fig. 1. By deciding values for $m$, $n$, and M, the memory compiler determines the aspect ratio of the memory and how many bitcells have to be muxed together. Let us consider an example with a datawidth of 64 bits and a depth of 128 locations, i.e., a memory that contains 8Kbits. The address A is 7 bits long, from which {A0, A1} index the columns while {A2, A3, A4, A5, A6} index the rows.

The column mux ratio $m$ plays a crucial role in a memory array as it represents the number of memory cells that are connected to a shared bitline. The choice of $m$ involves a trade-off between density, access time, and power consumption. A higher column mux ratio increases memory density because more cells can be packed into a given area. However, it also introduces larger capacitance and longer bitline lengths, leading to slower access times and potentially higher power consumption. On the other hand, a lower column mux ratio improves access time.

The location of the SRAM macro within the chip is determined by the overall floorplan. In our test chip, we have utilized 11 SRAMs with different possible orientations, as depicted in Figure 1. The default orientation is denoted as R0, representing a rotation angle of zero degrees. The notation MX signifies mirroring along the x-axis, R270 refers to a rotation of 270 degrees, R90 represents a rotation of 90 degrees, and MY90 signifies mirroring along the y-axis followed by a rotation of 90 degrees (all rotations mentioned here are anti-clockwise).

In SRAM-based PUFs, the combination of bitcells forms the response data. This response data can be evaluated by a number of metrics. The reliability metric measures the ability of a PUF to consistently reproduce its output response, independent of temperature variations and fluctuations in operating voltage. An ideal PUF should produce the same output in response to a given challenge, regardless of the environmental and operational conditions. The reliability of a PUF can be assessed by evaluating its within class hamming distance (WCHD), which is the fractional hamming distance between measurements taken at various conditions during reconstruction and a reference initial measurement (enrollment).

SRAM-based PUFs leverage entropy from process variations to build unique fingerprints for each identically fabricated chip. For entropy, one important parameter is the bias pattern that is linked with the PUF’s physical characteristics. The response data often displays a consistent bias towards either a logical zero or one at given intervals. This bias cannot be easily determined by calculating the fractional hamming weight, which measures the percentage of ones in the raw output response. This recurrent phenomenon is usually referred to as the bias pattern.

The biased SRAM-based PUFs will show higher auto-correlation values compared to non-biased devices. We select the SRAM-based PUF with the highest auto-correlation per SRAM-based PUF’s design and run Fast Fourier Transform (FFT) on the auto-correlation. The auto-correlation has some periodic effect, and the period corresponds to the width of the bias pattern. Entropy in SRAM-based PUF is derived by inserting the Masked Hamming Weight (MHW) into min-entropy formula, and MHW is calculated through the percentage of ones in the output response after an XOR operation with the bias pattern [11].

Prior to presenting our bias-related analysis, we will examine three important parameters: WCHD, MHW, and entropy. These parameters provide valuable information on the behavior and characteristics of the SRAM-based PUF. To start this, we merged data from 50 chips and evaluated the corresponding metric for each SRAM measurement. A summary of the results is presented in Table 1 where the first column lists the type of memory, and the subsequent columns are WCHD, MHW, and entropy. The WCHD values, which are below 10%, indicate a high level of reliability in the SRAM-based PUFs. Ideally, the MHW value should be around 0.5, and the results in the second column of Table 1 closely align with the ideal value. The entropy values are derived from the MHW values and also align well with the expected entropy levels. Furthermore, the entropy values obtained in our study were found to be comparable to those reported in [9]. The entropy values reported in [10] are slightly higher but their analysis is based on an older technology node, making a fair comparison challenging. Overall, the results confirmed that our SRAM-PUFs behave as expected and in line with previous studies.

Next, the analysis seeks to determine the impact of bias patterns on the SRAM-based PUFs over varying sizes, mux selection ratios, memory types and orientations. We found that, for this chip, the location of the memory on the floorplan has no impact on its functionality. However, when deciding how to arrange the floorplan, a designer may choose to rotate a memory to obtain better routability. Indeed, memory orientation affects the bias direction (BD). To start the analysis, the start-up pattern of SRAMs P₅_a, P₆, P₂_a and P₂_b are plotted in Fig. 3. One can visualize the biasing patterns that we will explain in the following results. The response vectors are concatenated into valid binary data from each row into a one-dimensional vector to determine the bias pattern. Next, we compute each auto-correlation for each chip (but only on the first measurement). The correlation between the MHW for all 50 chips is depicted in Fig. 4. Notably, the direction of correlation varies from one SRAM-based PUF to another when considering P₁_a as the baseline. For example, if we compare the correlation peaks for the baseline and P₂_b in Fig. 4 then the peaks are opposite; thus, we report the bias direction as negative. A summary of the relationship between the memory orientation and the bias correlation direction is listed in the last two columns of the Table. 1.

Observation 1: The bias pattern between different sizes is influenced by the data width, but it does not affect the direction of the bias pattern. The data width (word size), bias pattern, and the number of instances for different SRAM-based PUF instances are listed in the last three columns of Table 1. For instance, consider two identical memories, P₂_a and P₂_b. Despite their identical nature, these memories exhibit different bias directions. One memory may have a positive bias direction, while the other may have a negative bias direction.

Observation 2: Overall, the change in mux ratio causes the different aspect ratios, which have different bias patterns from 1024$\times$32_mux8 and 1024$\times$32_mux16. So, the larger mux ratio has an impact on the bias pattern. The identical SRAM-based PUFs have an identical bias pattern. On the other hand, the column mux ratio does not influence the direction of the bias pattern.

Observation 3: The use of fast and slow memories do not have any connection with the width of the bias pattern. Additionally, they are also not related to the direction of the bias pattern. In other words, the use of different bitcells does not translate into different bias widths or directions.

Observation 4: However, it is important to note that SRAM-based PUFs may display an alternating bias pattern, which is a result of the internal structure of SRAMs. As discussed in Section Background, the SRAM macro consists of two halves: one on the left and the other on the right. This arrangement leads to an interesting observation: the initial 32 bits of P₁_a and P₁_b tend to skew towards zero, followed by an alternating pattern of 64 bits.

Observation 5: It is confirmed that two memory orientations, namely R270 and MY90, show a negative biasing direction when compared to the other memories.

Observation 6: It has been confirmed that the bias pattern direction observed in SRAM-based PUFs is not influenced by factors such as power planning and the overall floorplan of the chip, except for considerations specifically related to orientation.

Observation 7: Intra-die process variation exhibits uniqueness between individual dies, and thus, it does not contribute to the direction of the bias pattern. We further confirm that all chips come from the same wafer and have not been rotated on the MPW reticle.

According to observations 1-7, the direction of the bias pattern cannot be affected by varying sizes, mux ratios, memory types, memory structure, or process variations. The orientations are the only factors that determine it. We make the following hypothesis to potentially explain the direction of the bias pattern.

Hypothesis 1: This effect emanates from the orientation of the bitcells themselves. The R90 orientation of the SRAM positions the bitcells vertically compared to the R0 orientation. When comparing the R90 orientation as a reference, the R270 and MY90 orientations flip the left and right bitcell arrays as illustrated in Fig. 1. This means that the placement direction of the bitcells associated with the first address of the SRAM becomes reversed. In other words, the direction of the bitcell placement linked to the first address of the SRAM becomes the opposite in these orientations.

Hypothesis 2: Understanding the impact of doping variations on the bias pattern is crucial for analyzing and mitigating their effects in SRAM-based PUFs. During the lithography process, the doping of transistors in SRAM cells plays a crucial role in their behavior. Although the process aims for uniformity, variations in doping can occur due to the limitations of the fabrication equipment [12]. The machine moves along the x-axis, doping the transistors as it progresses from left to right or right to left. It then steps up and continues the doping process until all transistors are treated. These doping variations have an impact on the initial state and stability of the SRAM cells. The stability of an SRAM cell is typically evaluated using the concept of static noise margin (SNM), which represents the minimum noise voltage required to flip the state of the bitcell. In SRAM cell design, the width-to-length (W/L) ratios of the load transistors and access transistors are often set to be as close to 1.0 as possible. The ratio of the driver transistor’s W/L to the access transistor’s W/L is known as the cell ratio, which determines the cell’s stability and size [12]. The doping variation directly affects the W/L ratio, potentially leading to variations in the SNM value. When considering the doping effect, transistors along the vertical axis experience more significant variations compared to adjacent transistors along the x-axis. These doping variations impact all SRAM-based PUFs to some extent. However, specific orientations, such as R270 and MY90, exhibit a distinctive negative bias pattern. In these orientations, the transistor arrangement becomes reversed or opposite to the baseline SRAM-based PUF’s orientation. This is the main finding of our work.

Our experiments revealed that the orientation affects the bias direction significantly. This observation could prove useful for designing smart error correction algorithms for SRAM-based PUFs. Regarding the evaluation characteristics of the SRAM-based PUFs, our findings are consistent with prior research, indicating that our SRAMs are representative. Nonetheless, our study presents a useful contribution to the field of PUF research and highlights the importance of careful physical implementation when designing SRAM-based PUFs.

This work has been partially conducted in the project “ICT programme” which was supported by the European Union through the ESF. It was also supported by EU’s Horizon 2020 R&I programme under Grant Agreement No 872614 (SMART4ALL).