High-Efficiency Harmonically-Terminated Diode and Transistor Rectifiers

In Fig. 1, a sinusoidal microwave power source with voltage magnitude $V_{s}$ and impedance $R_{s}$ drives the rectifying element of resistance $R(v)$ above. The DC load seen by the rectifying element is $R_{DC}$ while the load at the fundamental frequency $f_{0}$ and successive harmonics is set by the matching network. Assume the matching circuit presents $R_{s}(f_{0})$ to the rectifying element with all subsequent harmonics terminated in short circuits. This is equivalent to the harmonic terminations for a canonical reduced conduction angle power amplifier. This class is useful for Schottky diode rectifiers because these diodes have nonlinear junction capacitance. Short-circuiting the harmonics fixes the harmonic terminations at the intrinsic diode by shorting this junction capacitance.

When the incident RF voltage at the ideal rectifier swings negative, it is clipped at zero given (1). The enforced harmonic terminations force the voltage waveform to contain only a DC and fundamental frequency component. Therefore, a DC component must be produced by the rectifying element such that the voltage waveform maintains its sinusoidal nature. The voltage across the rectifying element can now be expressed as

where $V(f_{0})$ is the fundamental frequency component of the voltage across the rectifying element, $V_{DC}$ is the DC component, $V_{DC}=V(f_{0})$ and $\theta=2\pi f_{0}t$. The current waveform contains infinite frequency components, and can be written as

where $I_{DC}$ is the DC current and $\delta(\theta)$ is the Dirac delta function. When all available input power $P_{in}$ is delivered to the rectifier, the fundamental frequency component of the current through the rectifying element $I(f_{0})$ is

and, since there is no mechanism by which the rectifier itself can dissipate power ($R_{on}=0$ at this point), all of the available input power must be dissipated in the DC load and the conversion efficiency is 100%. Therefore,

Substituting in (5) and rearranging gives the expression of the current at the fundamental input frequency and the DC rectified current, which is $I(f_{0})=2I_{DC}$. When all available input power is delivered to the rectifier, the RF-DC conversion efficiency is 100% because the rectifying element is ideal and cannot dissipate power itself. In order for all available input power to be delivered to the rectifier, it is straightforward to show that the DC load must be set relative to the fundamental frequency load as

A harmonic balance simulation of an approximately ideal rectifier with short-circuited harmonic terminations was performed in Microwave Office^® using the SPICE diode model with no parasitics (PNIV) as the rectifying element. The device temperature was set to $1^{\circ}$ K to approximate an ideal switch. The fundamental frequency excitation was set to 1 W at 1 GHz with the first 200 harmonics terminated in short-circuits. The diode was presented with 50 $\Omega$ at the fundamental frequency and the DC load was swept from 5 $\Omega$ to 200 $\Omega$. The simulated data is then normalized to generalize the simulation results. The ideal time-domain current and voltage waveforms across the diode are shown in Fig. 2 with the RF-DC conversion efficiency as a function of $R_{DC}/R_{s}(f_{0})$ for varying rectifier on-resistance shown in Fig. 3. It is clear that the mechanism of operation in the ideal case agrees with the theory presented above. The reduction in RF-DC conversion efficiency when the DC load is not set according to (7) is due to impedance mismatch, and is given by

Consider again the rectifier circuit shown in Fig. 1 and assume that all even harmonics are terminated in open circuits, while all odd harmonics are terminated in short circuits. This set of harmonic terminations is the same as for a class-F^-1 amplifier, therefore this rectifier will be referred to as a class-F^-1 rectifier. The fundamental frequency component of the voltage across the rectifying device is given by

During the second half of the RF cycle, it is evident from (1) that the voltage across the rectifying element must be zero. This condition must be met through the addition of DC and only even harmonic voltage components, and therefore the voltage waveform is expressed as

A Fourier expansion of (10) expresses the DC component of the voltage waveform as

In the first half of the RF cycle, the current through the rectifying element is zero, given (1). This condition is met through the addition of a DC current and odd harmonic current components. With the current direction as in Fig. 1, the DC component of the current must be positive. Therefore, in the first half of the RF cycle, the remaining harmonics must sum to a constant value equivalent to the negative of the DC component. Since the function which is the sum of the remaining harmonics is odd, the second half of the RF cycle must sum to the DC component, and the current is given by

The DC component of the current waveform Fourier expansion is found to be

The DC load consistent with (10) and (12) is given by

The conversion efficiency, defined as the ratio of the DC power dissipated in the load resistor to the available fundamental frequency RF power, is evaluated as

Therefore, the ideal half-wave rectifier converts all available RF power to DC power if the the DC loading resistance set to the value given in (14). The RF-DC conversion efficiency as a function of $R_{DC}/R_{s}(f_{0})$ was simulated in Microwave Office^® for varying rectifier on-resistance and is shown in Fig. 4. The harmonic balance settings were identical to those used for the class-C rectifier above. The peak efficiency as a function of on-resistance is higher than for the class-C rectifier, although the efficiency degrades more quickly when the non-ideal DC load is applied.

The waveforms including parasitic on-resistance and threshold voltage are next investigated assuming the rectifier impedance from (2). The time domain voltage and current waveforms are approximated as

As an example, Fig. 5 shows the current and voltage waveforms for a specific set of non-ideal parameters ($V_{tr}=0.7\,\textrm{V}$, $V_{max}=20\,\textrm{V}$, $I_{max}=200\,\textrm{mA}$, and $R_{on}=5\,\Omega$). When the device is conducting current, it creates a voltage drop across the on-resistance which is constant due to the constant current. If the on-resistance were zero, the only difference between the waveform in (16) and the ideal voltage waveform would be the minimum value, which would be $-V_{tr}$ rather than zero. The values of $\theta$ at which the transition between the conducting and non-conducting regions occurs are found to be

The DC and fundamental frequency values of the voltage and current waveforms can be found through a Fourier analysis using the transition points in (18). The first Fourier coefficient of $v(t)$ gives the DC component of the voltage, which can be derived as

The fundamental frequency voltage is found from $V(f_{0})=a_{v}+jb_{v}$, where

and $b_{v}$ can be reduced to

Similarly, the DC component of the current waveform is found to be

The fundamental frequency current $i(t)=a_{i}+jb_{i}$ has $a_{i}=0$ and the coefficient $b_{i}$ can be shown to be equal to

The input power at the fundamental frequency is found from

Substituting (21) and (23) into the above results in

where $k$ is defined as

Solving for $I_{max}$ as a function of $P_{in}$ when $R_{on}$ is non-zero after some arithmetic results in two solutions, one of which is negative. The positive solution for the maximal current is

with $\alpha=V_{max}\left(\arcsin\left(\frac{V_{tr}}{V_{max}}\right)+\frac{\pi}{2}+k\frac{V_{tr}}{V_{max}}\right)$.

In the case where $R_{on}$ is zero, (27) simplifies to

Note that in the case of an ideal rectifying element, $k=1$ and $V_{tr}=0$, therefore

Now that $I_{max}$ is fully expressed given known rectifier parameters, $V_{DC}$ and $I_{DC}$, $V(f_{0})$ and $I(f_{0})$ may be calculated, and from this, the DC load and the load at fundamental frequency determined from the following expressions:

The negative impedance in (31) indicates that power is delivered to the rectifying element and gives the impedance of the source delivering power to the rectifying element. The rectifier efficiency is given by

To understand the usefulness of the presented theory, assume the rectifying element has the following parameters: $V_{max}=10$ V, $R_{on}=5$ $\Omega$, $V_{tr}=0.7$ V and $P(f_{0})$ = 1 W. First, (27) is used to calculate $I_{max}=456.7$ mA. Next, the DC voltage and current are evaluated using (19) and (22), respectively, to give $V_{DC}=1.75$ V and $I_{DC}=218.2$ mA. The fundamental frequency voltage and current Fourier coefficients are then calculated to be $V(f_{0})=6.896$ V and $I(f_{0})=-290$ mA, respectively. The DC and fundamental frequency resistances are then calculated using (30) and (31) to be $R_{DC}=8.02$ $\Omega$ and $R(f_{0})=23.77$ $\Omega$, respectively. The efficiency is then calculated using (32) to be $\eta$ = 38.18 %. If the input power is selected as 0.1 W rather than 1 W, the resultant efficiency is 72.43 % instead. A specific rectification device will always have an approximate input drive level at which it can be most efficient, just as with power transistors in power amplifiers. To maximize efficiency, the goal is always to minimize the amount of power dissipation in the on-resistance of the rectifying element and maximize the power dissipated in the DC load resistor.

A 2.14-GHz power amplifier, pictured on Fig. 8, is designed using the Triquint TGF2023-02 GaN pHEMT [gan_pa_letter]. Class F^-1 harmonic terminations are implemented at the second and third harmonic. The performance of the PA, illustrated in Fig. 9, was characterized at 2.14 GHz with a drain voltage bias of 28 V and a bias current of 160 mA. The PA exhibits a PAE of 84% with an output power of 37.6 dBm and a gain of 15.7 dB under 3 dB compression. The same PA design was used for rectifier measurements as shown in Fig. 10. The PA is connected to an input RF source at the drain, with the drain supply disconnected. The gate terminal is biased, and connected to an impedance tuner, converting the two-port transistor PA to a one-port rectifier, corresponding to the generalized schematic of Fig. 1.

The class-F^-1 power amplifier described above is fully characterized in large signal in a rectifier configuration with the setup shown in Fig. 10. The commercial time-domain large signal measurement instrument is a VTD SWAP four-channel receiver [SWAP]. In order to acquire time domain waveforms at the reference plane, an 8 error term model calibration similar to the one performed for LSNA (Large Signal Network Analyzer) measurements is applied. After an absolute VNA-like calibration [verspecht], the RF voltage and current waveforms at the input (V1 and I1) and at the output (V2 and I2) of the DUT are measured at the coaxial reference plane. In this case, the RF input is the drain port of the PA, while the RF output is connected to the gate port. Thus, performing a load pull on this device consists of varying the load at $f_{0}$ at the RF gate port of the PA with a passive tuner. This kind of measurement is similar to large signal characterization of switch devices recently reported in [switch, faraj_arftg_2012]. The gate DC path is connected to a power supply so the gate bias can be varied. The drain DC bias is the output of the rectifier and is connected to a variable resistance $R_{DC}$, and the DC voltage across it is measured with a voltmeter. The DC current is then found from the value of $R_{DC}$ from (30). During the measurement, several parameters are varied systematically: the RF load impedance applied at the PA gate port $Z_{g}(f_{0})=V_{g}(f_{0})/I_{g}(f_{0})$; the resistor in the DC drain output $R_{DC}$; and the gate bias voltage $V_{GS}$. The conversion efficiency of the rectifier and the DC power delivered at the drain output of the rectifier $P_{DC}=V_{DC}\cdot I_{DC}$ are measured as these parameters are varied, and as a function of input power at the drain port $P_{in}(f_{0})$.

The measurements of the rectifier are performed in self-synchronous mode, i.e. there is no input RF power incident externally into the gate port of the PA, unlike in previous transistor rectifier work [JoseIMS-rect, Kaz]. The following parameters are varied in order, while keeping the other parameters constant and sweeping the input RF power at the drain port, and the results are described in the same order:

1. 1.

   RF impedance at the gate, $Z_{g}$;

2. 2.

   load resistance at drain bias output, $R_{DC}$;

3. 3.

   gate DC bias, $V_{GS}$.

The gate load-pull was performed to determine the optimum impedance for maximum efficiency with a constant resistive DC load of 98.5 $\Omega$ (nominally 100 $\Omega$) and a constant transistor gate bias in pinch-off of -4.4 V. The RF signal is coupled from the drain to the gate matching network through the feedback capacitance $C_{gd}$, and thus the precise impedance presented at the gate of the transistor is imperative to achieving high efficiency. Fig. 11 shows the time-domain voltage and current waveforms measured at the drain and gate RF port of the amplifier when the RF input power at the drain port is swept from 11 dBm to 42 dBm. These values are chosen because the rectifier in PA operation gives up to 42 dBm output power. The feedback signal present at the gate allows for the rectifier to operate in self-synchronous mode without any additional control signal. Unlike in the synchronously driven case where an external generator is connected to the gate, here the impedance presented at the gate is always passive (inside the Smith chart), keeping the device in a safe operating mode.

Measured RF-DC conversion efficiency is shown in Fig. 12 for four different RF gate impedances. A maximal conversion efficiency of 85% is achieved with a DC output voltage of 36 V and an input power at the drain of 42 dBm with $R_{DC}=98.5\,\Omega$. This peak efficiency is for a RF gate load of around 230 $\Omega$ (green hexagon in the Smith chart in Fig. 12), which is the highest impedance that was achievable with the specific tuner in the setup. For the low gate impedance (red triangle in the Smith chart), the efficiency is significantly lower. By observing the gate current (Fig. 12d), it can be seen that for a low RF gate impedance, the gate diode turns on at around $P_{in}=25$ dBm. Since the input power cannot be increased much beyond this point to avoid breakdown, this limits the DC voltage at the output to around 4 V. For the gate impedance with highest efficiency (green line with hexagon symbol), the gate diode is off for input drain powers below 41 dBm, allowing for high DC voltage output.

After the optimal gate impedance for highest efficiency was obtained, a power sweep for three different $R_{DC}$ values in the drain output was obtained. From Fig. 13, a maximal efficiency of 85% was measured for a DC resistive load of 98 $\Omega$ while an efficiency drop of 13% was observed for a DC load of 21 $\Omega$ with 40 dBm input power. As expected, the DC output voltage decreases from a maximum 30 V for $R_{DC}=98$ $\Omega$ at 40 dBm input power, to a maximum of 13.4 V for $R_{DC}=21$ $\Omega$ with the same input power. It is interesting to see how the input impedance of the rectifier at the RF drain port approaches 50 $\Omega$ as the input power increases, Fig. 14. This is expected, since the PA was designed for maximal saturated power delivered into a 50 $\Omega$ load. This again points to the similarities between the same circuit operated as a power rectifier and a power amplifier.

Finally, the effect of the gate bias $V_{GS}$ on the rectifier efficiency, output voltage and input impedance was investigated. The gate impedance in this case was set for highest efficiency (230 $\Omega$), and a DC load of 58 $\Omega$ was selected in order to protect the transistor from high drain voltages that occur for the 98 $\Omega$ load that corresponds to the highest efficiency. The measurements were performed for six different values of gate bias $V_{GS}$ as shown in Fig. 15. With $R_{DC}=58\Omega$, a maximum efficiency of 83% was obtained with the transistor biased deeply into the pinch-off region with $V_{GS}=-4.4$ V, and a drop of only 3% was measured for $V_{GS}=-3.5$ V. Furthermore, the gate bias has a minimal impact on the output DC voltage or on the drain impedance.