DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems

Since the charge and discharge cycle – an intrinsic characteristic of energy harvesting devices – may occur more than hundreds of times per second, NV elements can maintain their computation state and ensure forward progress in the presence of unpredictable energy failures. Critical difficulties encountered in prior research include the requirement for intricate software that lacks scalability, performance overhead introduced by NVM components, and system inconsistencies. In this section, a co-design methodology is introduced to push the boundaries of intermittent computing. This methodology entails the development of a novel architecture and software strategy that minimizes overhead while maximizing forward progress. Figure 1 shows the design flow of our systematic Design Exploration of Intermittent-Aware Computing (DIAC) methodology to address power failure with minimum performance overhead, offered by three complementary procedures:

Batteryless systems can be broadly categorized into two primary types. The first category can complete all computations when the battery is fully charged. Conversely, the second type has inadequate capacitor energy storage to satisfy all computations. For the second type, storing intermediate registers in NVMs is imperative. Herein, all operations, namely sense (Se), compute (Cp), transmit (Tr), sleep (Sp), and backup (Bk), are divided into atomic operations, which are executed uninterrupted. These atomic operations are determined based on the system’s maximum storage power and should only begin when sufficient power is available. We will iteratively use three policies to determine optimal atomic operations to maximize efficiency. The finite state machine (FSM) of the system offering the core operations of an IoT node, sense, compute, transmit, and sleep states is depicted in Fig. 3 (a). Initially, the system is in Sp and reverts to this state after completing each atomic operation to conserve power for the next process. Integrating DIAC’s produced design with the proposed FSM forms an intermittent-aware sensor node, ensuring resilience against power interruptions, shown in Fig. 3(b).

A detailed description of the required steps is illustrated in Algorithm 1. The algorithm starts with the main while looping in line 3. This loop runs according to the interval value in line 33. As this loop is executed, the system’s state changes depending on the Reg_Flag and energy level (lines 6-11). The system has four threshold voltages for each state (Th_State), e.g.,Th_Cp, along with two more thresholds Th_{Safe_Zone} and Th_Off. The system can perform tasks in each state if and only if criteria, including Reg_Flag and enough power to complete the desired operation (Energy$>$Th_State), are satisfied. Once the system transitions to either the Cp or Tr, it will stay in this state until the power drops below the threshold defined by Th_{Safe_Zone} (lines 17 and 27). The Safe_Zone threshold creates a narrow range that lies between the exit points of Cp or Tr and the beginning of Bk state. The system can harvest further energy within this range, allowing it to restore to its prior state instead of reverting to Bk. The transition to the next state is determined by modifying the value of the Reg_Flag. However, this progression can be halted at any state by setting the Reg_Flag to ‘0b000’. For example, in Cp, the Reg_Flag stays unchanged until the computation is done. Then, according to the computation result (lines 20-23), the Reg_Flag is set to Tr or Sp and exits the loop. During either Cp or Tr, when the power level falls below the Safe_Zone, the system reverts to Sp (lines 25-32). There are two interrupt routines in our system. The first interrupt is for the Timer (line 34), which is the maximum sampling rate of the system. However, it is important to note that this frequency can be reduced depending on the system’s power. The second interrupt (Power) is generated by the power management unit (line 38). Suppose the total energy of the system is less than the threshold energy required for backup. In that case, the power management unit triggers an interrupt, and the backup unit stores all the necessary intermediate registers based on the register flag (Reg_Flag). Since the energy of the system reduces in the Sp state (due to the standby energy), the system requires an interrupt to change its state to Bk.

As previously noted, Policy3 simultaneously provides acceptable resiliency and efficiency. Thus, we utilize it as a replacement policy and the principal methodology in this section. Figure 2(d) shows an example of this approach where the upper and lower limits for power consumption are set at $25$mJ and $20$mJ per operand, respectively. Consequently, operands consuming more than $25$mJ of power must be divided, while those using less than $20$mJ should be combined. Thus, F_5-8 are merged to be represented by F₁₃. Conversely, F₂ is broken down into smaller operands, i.e., F_9-11. This step is followed by creating a dictionary based on the operands’ number of inputs and outputs, delays, and power consumption. To accurately estimate the power and delay of each operation, DIAC harnesses the output from HSPICE, considering delay, static, and dynamic power for each operand, which comprises multiple gates. We then devised a mathematical model to meet diverse needs and estimate design-time evaluation parameters before run-time. We approximated the dynamic energy using $\approx 2\times\sum_{i=0}^{n}delay_{i}\times dynamic\_power_{i}$, where $n$ represents the total number of gates in an operand, and the delay is determined when both input and output equal ${V_{DD}}\over{2}$. For a more accurate energy consumption estimation, this delay is doubled. It is essential to highlight that while one gate is in switching mode, other gates remain inactive without any activities. Therefore, the power consumption of these inactive gates is determined by the critical delay path (CDP) multiplied by the total number of gates ($\approx CDP\times\sum_{i=0}^{n-1}static\_power_{i}$), excluding the currently active gate. A system-level in-house framework is developed to verify our approach’s functionality. Firstly, we implement a design by traversing its NV-enhanced tree generated by DIAC and concerning the system’s parameters, including peripherals, using HSPICE in the 45nm NCSU PDK library. The memory controller and registers are designed and synthesized by Design Compiler. Afterward, we incorporated the results from circuit-level assessments and extensively modified CACTI at the architecture level. Next, we integrated the architecture with the proposed FSM and exported the performance to an in-house cross-layer framework, taking the CACTI output and application netlist as the inputs. At the application, we evaluated the performance of our proposed technique in the presence of power outages using various benchmarks. To incorporate the behavior of intermittency into our study, we adopted a methodological approach that involved simulating an intermittent power source characterized by a predetermined sequence of voltage levels that cyclically repeat. To accurately represent the behavior of intermittent power, we introduced a virtual energy source within our simulation framework, designed to mimic the functionality of a battery. This virtual energy source is responsible for accumulating energy during power availability and deducting energy consumption during periods of power unavailability. Throughout the simulation process, we closely monitored several key parameters to ensure an accurate representation, including power/voltage levels, power availability, and the level of the virtual energy source. Monitoring is achieved by observing the behavior of the power source and virtual battery, as well as tracking the power consumption associated with various computational operations. In the system, a capacitance of $2$mF is considered, and an operational voltage of 5V is used. Therefore, the system can store a maximum of E_MAX $=25$mJ of energy. Herein, we assume that the sense, compute, and transmit operations consume $2$mJ, $4$mJ, and $9$mJ, respectively, all with a $\pm\%10$ uncertainty. Furthermore, the Th_{Safe_Zone} region exceeds the backup threshold by $2$mJ. In this zone, the system enters sleep mode without requiring a backup. However, if the battery energy drops below Th_Bk, the NVMs save all essential registers.

Figure 4 illustrates the energy (E_Batt) stored in the capacitor concerning the system’s charging rate. In , the charging rate surpasses the system’s needs. Consequently, the energy stored occasionally reaches its maximum capacity of E_MAX, i.e., $25$mJ. This allows the system to operate at peak performance. Conversely, in , the charging rate is insufficient to meet the system’s demands. The system remains in the Sp state until E_Batt surpasses Th_Cp. It then transitions to either Cp or Tr states. During this phase, the system continues operations until the energy drops below Th_{Safe_Zone}. In , a sudden decline in the charging rate is noted, falling below Th_Bk. Consequently, the system backs up its registers to the NVMs. Following the backup in , a sustained low charging rate causes E_Batt to drop beneath Th_Off, resulting in a complete system shutdown. Upon accumulating sufficient power, the system then retrieves register data based on the NVM values. As previously explained, the Th_{Safe_Zone} threshold is crucial in minimizing NVM writes. As exemplified in , the system enters this zone thrice, maintaining its state in Sp. Throughout these three instances, since E_Batt never fell below Th_Bk, no energy-intensive NVM writes were needed. Subsequent efficient energy harvesting allowed the system to transition back to an active domain, fetching states directly from volatile storage and the Reg_Flag. A different scenario unfolds in , where the charging source is interrupted, prompting the system to revert to the Sp state. Despite being in this state, a minimal leakage current persists, causing the system’s energy to fall below Th_Bk. This triggers a backup process. But the charging is restored before a complete power outage, enabling the system to resume operations. Herein, there’s no necessity to fetch register values from the NVMs.

In this section, the developed design tool, including DIAC and the FSM, is leveraged to implement large-scale circuit benchmarks, including ISCAS-89, ITC-99, and MCNC. To evaluate DIAC performance using the developed framework, the power-delay-product (PDP) values for the four schemes are considered. The NV-based method operates similarly to conventional checkpointing, where flip-flops (FFs) are replaced by the NV-FFs to store states. It provides the highest resiliency at the cost of significant overhead. The second compared technique is NV-Clusting, presented in [7]. In this approach, the authors introduced a new concept, logic-embedded flip-flop (LE-FF), which can realize Boolean logic functions and an inherent state-holding capability. To make the evaluation more comprehensive, we have considered two DIAC-based implementations, excluding and including Th_{Safe_Zone}, denoting DIAC, and optimized_DIAC designs, respectively. According to subsection 2.B, this state allows us to reduce power consumption and delay by reducing the number of NVM writes required. Because of this, the optimized_DIAC process significantly reduces the number of NVM writes as a costly operation. It is worth noting that the safe zone varies based on the harvested energy. Figure 5 depicts the PDP results for all the mentioned approaches. For various ISCAS-89, ITC-99, and MCNC benchmark circuits, these results exhibit an average of 36% (25%), 41% (33%), and 34% (28%) PDP improvements, respectively, for the DIAC_based designs compared to NV-based (NV-clustering) implementations. Further PDP improvements are achieved by using the optimized_DIAC methodology, which provides up to 61, 56, and 38 percent average PDP improvements compared to NV-based, NV-clustering, and DIAC approaches, respectively. The benefits are achieved because of the optimal NVM write operations.

Two assumptions are considered when assessing the DIAC methodology:(1) There is never enough energy in the system to complete a process (instance). This means that using conventional CMOS-based designs without NVMs will not work. To ensure this condition, if a benchmark circuit, e.g., s27, consumes less energy than battery capacity, it is rerun multiple times till the total energy exceeds the capacity. Then, we considered all performed operations as one bigger and/or more complex task; (2) To make a fair comparison among different intermittent robust computing systems, the same NVM technology is leveraged. Extensive research has been conducted on designing NVMs using different NV elements, such as magnetic RAM (MRAM), resistive random access memory (ReRAM), ferroelectric random-access memory (FeRAM), and phase change memory (PCM). Due to the International Technology Roadmap for Semiconductors (ITRS) report, which identifies spintronic devices as capable post-CMOS candidates, we chose MRAM as our NVM technology. MRAM cells provide non-volatility, near-zero standby power, high integration density, and radiation-hardness features. Moreover, MTJs can be vertically integrated at the back-end CMOS fabrication process, resulting in lower interconnect energy losses and less area overhead. It is noteworthy that although varying NVM technology changes (reduces/increases) the enhancement, the overall improvement trend remains relatively stable. This is achieved because the DIAC approach optimizes NVM writes as an energy-hungry operation. For example, if ReRAMs replace MRAM cells, the optimized_DIAC exhibits higher efficiency than the other examined techniques because the ReRAM write consumes $\sim 4.4\times$ more energy than MRAM.