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Automatic Reconfiguration of Untimed Discrete-Event Systems

M. Macktoobian and W. M. Wonham
(Department of Electrical and Computer Engineering
University of Toronto
Toronto, ON, Canada M5S 3G4
Email: {matin.macktoobian,wonham}@scg.utoronto.ca)
Abstract

This work introduces a general formulation of the reconfiguration problem for untimed discrete-event systems (DES), which can be treated directly by supervisory control theory (SCT). To model the reconfiguration requirements we introduce the concept of reconfiguration specification (RS); here reconfiguration events (RE) are introduced to force a transition from one system configuration to another. Standard SCT synthesis is employed to obtain a reconfiguration supervisor (RSUP) in which designated states serve as the source states for RE. The reconfiguration problem itself is formulated as that of establishing guaranteed finite reachability of a desired RE source state in RSUP from the current state in RSUP at which a change in configuration is commanded by an external user. The solvability (or otherwise) of this reachability problem is established by backtracking as in standard dynamic programming.

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14(1.5,1) Published in “2017 14th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)”
DOI: 10.1109/ICEEE.2017.8108839

1 Introduction

Highly complex systems are typically composed of many components. A system configuration (mode) is implemented by a particular subset of the system’s components exhibiting a specific functionality. Dynamic reconfiguration is the automatic switching of the current configuration of the system to a new one commanded by the system’s external user (e.g., manager of a factory workcell). The importance of reconfiguration, in the case of complex systems, is two-fold. First, the model now embraces multimodal systems, thereby achieving multifunctionality through multimodality. Second, since reconfiguration enables switching from a faulty configuration to a sound one, the overall system’s reliability, and its robust response to faults, are each enhanced.

There have been extensive investigations into the notion of reconfiguration in the context of different complex systems such as power systems ([1, 2, 3]), embedded systems ([4, 5]), hybrid systems ([6, 7]), and manufacturing systems ([8]). Petri-net-based modeling of DES has also been employed to realize dynamic reconfiguration tasks. For example, [9] proposed a communication protocol to coordinate reconfiguration of software agents by coordination matrices. Many other applications of Petri nets could be cited of dynamic reconfiguration of complex systems (e.g., see [10]).

Moreover, some efforts have been applied to engineer reconfigurable DES. For instance, [11] recommended a coordinated approach to solve the problem; the technique stressed communication among the subsystems of the DES. It was further assumed that all subsystems are equipped with coordinators to manage the system reconfigurations. The virtual coordinator exchanges messages with subsystems separately, rather than subsystems intercommunicating directly. Whenever a subsystem desires to execute a global reconfiguration, it first requests permission of the coordinator. However, the approach seems not to be efficiently scalable.

Recently, the notion of state attraction [12] has been used to reconfigure DES by regular specifications. In particular, a coordination automaton (CA) is generated to weakly attract a required reconfiguration. The path from each initial state of CA to its marked state guides a particular supervisor to realize the required reconfiguration [13]. However, this approach is unable to reconfigure DES at any arbitrary state, and the synthesized CA is nondeterminstic including more than one initial state.

For the reconfiguration control of DES, SCT [14] has already shown promise. Recall that in SCT a supervisor is synthesized for given formal specifications in such a way as to be correct by design. In this spirit [15] addressed the dynamic rescheduling of a timed DES (or TDES) by use of a timed supervisor. In addition [16] proposed a method based on Petri nets and integer programming to optimize the cost of reconfiguration. The method uses linear constraints to synthesize deadlock-free supervisors by SCT.

This paper presents an automatic procedure to reconfigure DES by SCT dynamically. To this end, we introduce the notion of reconfiguration specification (RS) to model reconfiguration requirements; this specification is incorporated into the SCT supervisor synthesis in the usual way. The resulting supervisor not only realizes the behavioral specifications of the DES, but also switches between configurations when reconfiguration is commanded by an external system manager. Finally, it is necessary to know whether a desired reconfiguration is achievable from a particular state of the supervisor or not. At that point we apply a backtracking path-finding algorithm based on dynamic programming to collect all forcible paths (if any) that solve the intended reconfiguration problem.

The paper is organized as follows: Section 2 is devoted to preliminaries. Section 3 elaborates on the realization of the automatic dynamic reconfiguration by SCT. The new definition of RS is stated in Section 3.1. Section 3.2 provides the RSUP synthesis process. The reconfiguration problem is formally defined in Section 4.1. In Section 4.2 we describe the collection of forcible backtracking paths; the formal algorithm is presented Section 4.3. Section 5 illustrates the proposed method with an example, and conclusions are drawn in Section 6.

2 Preliminaries

SCT controls DES modeled by the Ramadge-Wonham framework [17, 18]. A DES is formally represented by a generator, say

G=(Q,Σ,δ,q0,Qm),\textbf{G}=(Q,\Sigma,\delta,q_{0},Q_{m}),

where Σ=Σc˙Σu\Sigma=\Sigma_{c}\dot{\cup}\Sigma_{u} is a finite alphabet of event labels, partitioned into the controllable event labels and the uncontrollable ones; QQ is the state set, assumed finite; δ:Q×ΣQ\delta:Q\times\Sigma^{*}\rightarrow Q is the extended partial transition function; q0q_{0} is the initial state; and QmQQ_{m}\subseteq Q is the subset of marked states. The closed behavior and the marked behavior of G are the languages

L(G):={sΣ|δ(q0,s)!}L(\textbf{G}):=\{s\in\Sigma^{*}|\delta(q_{0},s)!\}

and

Lm(G):={sL(G)|δ(q0,s)Qm}L_{m}(\textbf{G}):=\{s\in L(\textbf{G})|\delta(q_{0},s)\in Q_{m}\}

Here δ(q0,s)!\delta(q_{0},s)! means that δ(q0,s)\delta(q_{0},s) is defined. A supervisory control function for G is a map V:L(G)Γ\textbf{V}:L(\textbf{G})\rightarrow\Gamma, in which Γ={γPwr(Σ)|γΣu}\Gamma=\{\gamma\in Pwr(\Sigma)|\gamma\supseteq\Sigma_{u}\} is the set of control patterns. ‘G under supervision of V’ is written as V/G\textbf{V}/\textbf{G}.

Given a sublanguage MLm(G)M\subseteq L_{m}(\textbf{G}) we define the marked behavior of V/G\textbf{V}/\textbf{G} as Lm(V/G):=L(V/G)ML_{m}(\textbf{V}/\textbf{G}):=L(\textbf{V}/\textbf{G})\cap M. V is a marking nonblocking supervisory control (MNSC) for the pair (M,G)(M,\textbf{G}) if Lm(V/G)¯=L(V/G)\overline{L_{m}(\textbf{V}/\textbf{G})}=L(\textbf{V}/\textbf{G}). In practice, V is implemented by a supervisor, which can be taken as a generator SUP that represents the maximally permissive controlled behavior Lm(V/G)L_{m}(\textbf{V}/\textbf{G}) subject to a generator specification, say SPEC; we denote this computation by SUP = supcon (G,SPEC). For details see, e.g., [14].

Refer to caption
Figure 1: Generator of a binary RS

3 DES Reconfiguration

Refer to caption
Figure 2: DES reconfiguration process

3.1 Reconfiguration Specification

A reconfiguration requirement is a transition request to transfer the system from one configuration to another. The set of reconfiguration requirements associated with a DES is represented by the RS. As the first step, the following definition clarifies the notion of configuration (mode).

Definition \@upn1 [Configuration (Mode)].

Let G be a DES constructed by (synchronous product of) the collection of component sets CG={CGα|α}C_{\textbf{G}}=\{C_{\textbf{G}}^{\alpha}|\alpha\in\mathcal{I}\}, where \mathcal{I} is an index set. A configuration (mode) of G is a component set CG0CGC^{0}_{\textbf{G}}\subseteq C_{\textbf{G}} such that G operates as the corresponding synchronous subproduct, when the elements of CG0C^{0}_{\textbf{G}} and CGCG0C_{\textbf{G}}\setminus C^{0}_{\textbf{G}} are respectively active and inactive.

The source and destination configurations, corresponding to a reconfiguration task, are connected through a reconfiguration event (RE) which specifies a transition from the former to the latter.

Definition \@upn2 [RE].

Given DES G with component set CGC_{\textbf{G}}, let CG𝒜,CGCGC^{\mathcal{A}}_{\textbf{G}},C^{\mathcal{B}}_{\textbf{G}}\subset C_{\textbf{G}} be two configurations of G, where 𝒜\mathcal{A} and \mathcal{B} are the component sets which must be deactivated and activated respectively in the course of reconfiguration; then, RE σ𝒜,\sigma_{\mathcal{A},\mathcal{B}} must occur to trigger the reconfiguration task. We formalize this task as follows.

Definition \@upn3 [RS].

For a configuration CGC_{\textbf{G}}^{\mathcal{I}} of G, with components {Ga|a}\{\textbf{G}_{a}|a\in\mathcal{I}\}, let Σ\Sigma_{\mathcal{I}} denote the set of exactly the event (labels) appearing in the corresponding components, i.e.

Σ:={Σa|a}\Sigma_{\mathcal{I}}:=\bigcup\{\Sigma_{a}|a\in\mathcal{I}\}

For clarity we first consider the case of just two configurations, indexed by 𝒜\mathcal{A} and \mathcal{B}, and assume that reconfiguration requires switching either from CG𝒜C_{\textbf{G}}^{\mathcal{A}} to CGC_{\textbf{G}}^{\mathcal{B}}, with the system G initially in mode CG𝒜C_{\textbf{G}}^{\mathcal{A}}. As in Definition 2, bring in the corresponding switching events σ𝒜,\sigma_{\mathcal{A},\mathcal{B}} and σ,𝒜\sigma_{\mathcal{B},\mathcal{A}}. We define the RS as the DES

E:=(Q,Σ,δ,q0,Qm)E_{\mathcal{R}}:=(Q_{\mathcal{R}},\Sigma_{\mathcal{R}},\delta_{\mathcal{R}},{q_{0}}_{\mathcal{R}},{Q_{m}}_{\mathcal{R}})

where

  • Q:={q𝒜,q}Q_{\mathcal{R}}:=\{q_{\mathcal{A}},q_{\mathcal{B}}\}

  • Σ:=Σ𝒜Σ˙{σ𝒜,,σ,𝒜}\Sigma_{\mathcal{R}}:=\Sigma_{\mathcal{A}}\cup\Sigma_{\mathcal{B}}\dot{\cup}\{\sigma_{\mathcal{A},\mathcal{B}},\sigma_{\mathcal{B},\mathcal{A}}\}
    Note that Σ𝒜Σ\Sigma_{\mathcal{A}}\cup\Sigma_{\mathcal{B}} is disjoint from {σ𝒜,,σ,𝒜}\{\sigma_{\mathcal{A},\mathcal{B}},\sigma_{\mathcal{B},\mathcal{A}}\}.

  • δ(q𝒜,σ):={q𝒜ifσΣ𝒜,qifσ=σ𝒜,,\delta_{\mathcal{R}}(q_{\mathcal{A}},\sigma):=\begin{cases}q_{\mathcal{A}}~{}~{}~{}\text{if}~{}~{}~{}\sigma\in\Sigma_{\mathcal{A}},\\ q_{\mathcal{B}}~{}~{}~{}\text{if}~{}~{}~{}\sigma=\sigma_{\mathcal{A},\mathcal{B}},\end{cases}
    δ(q,σ):={qifσΣ,q𝒜ifσ=σ,𝒜,\delta_{\mathcal{R}}(q_{\mathcal{B}},\sigma):=\begin{cases}q_{\mathcal{B}}~{}~{}~{}\text{if}~{}~{}~{}\sigma\in\Sigma_{\mathcal{B}},\\ q_{\mathcal{A}}~{}~{}~{}\text{if}~{}~{}~{}\sigma=\sigma_{\mathcal{B},\mathcal{A}},\end{cases}
  • q0:=q𝒜{q_{0}}_{\mathcal{R}}:=q_{\mathcal{A}}

  • Qm:={q𝒜,q}{Q_{m}}_{\mathcal{R}}:=\{q_{\mathcal{A}},q_{\mathcal{B}}\}

EE_{\mathcal{R}} is depicted in Fig. 1.

It is obvious that, with some notational elaboration, this definition of EE_{\mathcal{R}} could be extended to an arbitrary number of distinct configurations and pairwise switchings among them, but we refrain from doing so here.

3.2 Reconfiguring Supervisor Synthesis

In general SCT synchronizes the plant DES G with its associated behavioral specification prior to synthesizing the supervisor which controls it. To synthesize RSUP we provide in this section an extended supervisor synthesis procedure in which the RS is taken into account.

The main idea is to treat the RS on the same footing as any other behavioral specification. The process is illustrated in Fig. 2.

We start by synchronizing all the components associated with G; here the operator ‘\parallel’ denotes synchronous product [19]. Then, G is synchronized with the RS EE_{\mathcal{R}} leading to the multimodal version of G, say GMode as follows.

GMode:=(||i=1nGi)||E\textbf{GMode}:=(||_{i=1}^{n}\textbf{G}_{i})||E_{\mathcal{R}}

Next, the global system specification is defined by the synchronization of the behavioral specification EE with all events of GMode. Finally, the reconfiguration supervisor is computed as:

RSUP:=supcon(GMode,[allevents(GMode)||E])\textbf{RSUP}:=\textbf{supcon}(\textbf{GMode},[\textbf{allevents}(\textbf{GMode})||E])

where the operator allevents returns a marked one-state DES selflooped with all the events of the argument. For details see, e.g., [14].

We emphasize that RSUP enforces both the behavioral and reconfiguration requirements of G.

In the next section we complete the design process by presenting an algorithm to solve the final reconfiguration problem.

4 Reconfiguration Solvability

We construct a backtracking algorithm that collects all forcible paths reaching a suitable target state of RSUP from an arbitrary current state. To this end, we first present the formal definition of the reconfiguration problem, then obtain the conditions for backtracking forcibility, and finally propose an algorithm to solve the problem.

4.1 Problem Statement

Especially when it is the intended response to some unexpected failure or emergency, reconfiguration could possibly be commanded from an arbitrary state in RSUP of the current (running) configuration. Thus the system must be forced onto a path or set of paths in the RSUP state space leading from the current state to one at which the desired reconfiguration event is defined. The question is then whether or not such a path (set) always exists and can be executed in timely fashion. We thus consider

Problem \@upn1 [Reconfiguration Feasibility].

Denote by qcq_{c} the state where RSUP currently resides, and let qrq_{r} be a state at which a desired reconfiguration event, say σr\sigma_{r}, is defined; namely δ(qr,σr)!\delta_{\mathcal{R}}(q_{r},\sigma_{r})! Subject to an appropriate specification of forcibility, determine the forcible path (set) from qcq_{c} to qrq_{r}.

We shall declare a path (set) forcible if it can be enforced using the standard SCT “technology” of controllable event disablement, with or without the possible additional use of preemption by a forcible event ([14], Sect. 3.8).

The following section describes how to obtain a forcible path (set).

4.2 Backtracking Forcibility

The algorithm is critically governed by the conditions which define forcibility of each backtracking step; if a backtracking step is forcible, then its event is appended to the current path.

We explain the backtracking forcibility conditions (BFCs) by a hypothetical search space as depicted in Fig. 3. We assess the forcibility of the backtracking from qrq_{r} to qiq_{i}. In other words, we plan to find whether σ\sigma contributes to an forcible path (from qiq_{i} to qrq_{r}) or not.

Let Σi={σ1,σ2,σ3,σ4,σ}\Sigma^{i}=\{\sigma_{1},\sigma_{2},\sigma_{3},\sigma_{4},\sigma^{\prime}\} be the set of defined events at qiq_{i}, competing with σ\sigma to occur. Let also Σi={σ}\Sigma_{i}=\{\sigma\} be the defined events transitioning from qiq_{i} to qrq_{r}. If any of the following four conditions hold, then backtracking to qiq_{i} is permissible, and σ\sigma is a solution to this problem:

BFC-1: Σi=\Sigma^{i}=\varnothing
There is no event competing with σ\sigma to occur at qiq_{i}. In other words, σ\sigma is the exclusive event which can occur at qiq_{i}.

BFC-2: (σΣi)σΣc(\forall\sigma^{\prime}\in\Sigma^{i})~{}\sigma^{\prime}\in\Sigma_{c}
If all of the Σi\Sigma^{i} events are controllable, then they can be disabled; therefore, σ\sigma can occur at qiq_{i}.

Refer to caption
Figure 3: The hypothetical backtracking scenario

BFC-3: [(σΣi)pr(σ,σ)][(σΣui)(σ′′Σi)]pr(σ′′,σ)[(\nexists\sigma^{\prime}\in\Sigma_{i})~{}\text{pr}(\sigma^{\prime},\sigma)]~{}~{}\wedge~{}~{}[(\forall\sigma^{\prime}\in\Sigma^{i}_{u})(\exists\sigma^{\prime\prime}\in\Sigma^{i})]~{}\text{pr}(\sigma^{\prime\prime},\sigma^{\prime})
Σi\Sigma^{i} is composed of both controllable and uncontrollable events. The first subformula says no competing event should be able to preempt σ\sigma. The second subformula asserts that each uncontrollable event must be preemptable by at least another event. Note that the binary relation pr(σ,σ′′)\text{pr}(\sigma^{\prime},\sigma^{\prime\prime}) holds if the forcible event σ\sigma^{\prime} can preempt σ′′\sigma^{\prime\prime} (see, section 3.9 of [14]). Furthermore, Σui\Sigma_{u}^{i} and Σci\Sigma_{c}^{i} represent the largest uncontrollable and controllable subsets of Σi\Sigma^{i}, respectively, where Σi=Σci˙Σui\Sigma^{i}=\Sigma_{c}^{i}\dot{\cup}\Sigma_{u}^{i}.

BFC-4: (σΣui)(σ′′ΣjΣj)[δ(qi,σ)=qjσ′′Σc(\exists\sigma^{\prime}\in\Sigma_{u}^{i})(\forall\sigma^{\prime\prime}\in\Sigma_{j}\cup\Sigma^{j})~{}~{}[\delta(q_{i},\sigma^{\prime})=q_{j}\wedge\sigma^{\prime\prime}\in\Sigma_{c}], where Σj\Sigma_{j} contains the event(s) transitioning from qjq_{j} and to qrq_{r}, and Σj\Sigma^{j} contains the event(s) transitioning from qjq_{j} to the other states.

This condition determines the succession of the uncontrollable events leading to a state containing only controllable events; since the controllable events can be disabled, both σ\sigma and σσ′′\sigma^{\prime}\sigma^{\prime\prime} are forcible paths.

We employ the foregoing conditions, as decision-making criteria, to solve the reconfiguration problem by a backtracking algorithm in the next section.

4.3 Reconfiguration Solvability Algorithm

Admissible paths can be collected by the Algorithm 1. The inputs are the target state, from which the backtracking starts; the source state, which is the algorithm’s goal to be visited; the state list of the supervisor, which is the search space of the problem including the target and source state; and a temporary list of incomplete paths initialized to empty, in which the potential solutions are stored, corresponding to each instantiation of the algorithm. The output is the collection of the found paths.

The algorithm keeps the track of the visited states and events. If it visits a state that is the destination of more than one event, the algorithm checks inductively the solvability of those branches.

Algorithm 1 Path Collector Algorithm (𝒫𝒞𝒜\mathcal{PCA})
1:
2:qrq_{r} \triangleright Target state
3:qsq_{s} \triangleright Source state
4:QTQ_{T} \triangleright State list
5:𝒫temp\mathcal{P}_{\text{temp}} \triangleright Temporary list of an incomplete path
6:
7:𝒫\mathcal{P} \triangleright Path collection  
8:if QT=Q_{T}=\varnothing then
9:     return 𝒫\mathcal{P} \triangleright All instances of 𝒫𝒞𝒜\mathcal{PCA} are terminated.
10:else
11:     𝒬{q|δ(q,σ)=qr}\mathcal{Q}\leftarrow\{q|\delta(q,\sigma)=q_{r}\}
12:     for each qi𝒬q_{i}\in\mathcal{Q} do
13:         Σi{σ|δ(qi,σ)=qr\Sigma_{i}\leftarrow\{\sigma|\delta(q_{i},\sigma)=q_{r}}
14:         Σi{σ|δ(qi,σ)!}Σi\Sigma^{i}\leftarrow\{\sigma|\delta(q_{i},\sigma)!\}-\Sigma_{i}
15:         if qi=qsq_{i}=q_{s} then
16:              𝒫append Σi to 𝒫temp\mathcal{P}\leftarrow\text{append }\Sigma_{i}\text{ to }\mathcal{P}_{\text{temp}}
17:              QTQT{qi}Q_{T}\leftarrow Q_{T}-\{q_{i}\}
18:         else
19:              for each σΣi\sigma\in\Sigma_{i} do
20:                  if (BFC-1 \parallel BFC-2 \parallel BFC-3 \parallel BFC-4)  then
21:                       𝒫tempappend σ to 𝒫temp\mathcal{P}_{\text{temp}}\leftarrow\text{append }\sigma\text{ to }\mathcal{P}_{\text{temp}}
22:                       QTQT{qi}Q_{T}\leftarrow Q_{T}-\{q_{i}\}
23:                       return 𝒫𝒞𝒜(qi,qs,QT,𝒫temp)\mathcal{PCA}(q_{i},q_{s},Q_{T},\mathcal{P}_{\text{temp}})
24:                  end if
25:              end for
26:         end if
27:     end for
28:end if

Line 1 defines the terminal case; if all states are checked, then the path collection will be delivered.

Line 4 gathers the states that have transitions to the current target state. The defined events at each found state are stored in two variables: variable Σi\Sigma_{i} which contains the event(s) transitioning from the found state qiq_{i} to the current state (Line 6); and variable Σi\Sigma^{i} which stores the event(s) transitioning from qiq_{i} to the other states (Line 7).

If qiq_{i} is the source state (Line 8), then a path is found. Hence, the recent found event is attached to the temporary solution, and the result is stored in the path collection (Line 9). Moreover, qiq_{i} is removed from the global list of unvisited states (Line 10). Otherwise, BFCs are checked with respect to the elements of Σi\Sigma_{i} and Σi\Sigma^{i} (Line 13). If any of these conditions holds, then the backtracking from the current state to qiq_{i} is authorized, thereby appending σ\sigma to the temporary solution variable (Line 14). Then, the global variable list is updated by removing qiq_{i} (Line 15), and a new instantiation of the algorithm is called according to the updated current state (Line 16). Note that both QTQ_{T} and 𝒫\mathcal{P} are global variables that can be read and modified by any instantiation of 𝒫𝒞𝒜\mathcal{PCA}.

Finally, Algorithm 1 can be incorporated appropriately into the final solvability checker function, i.e., Algorithm 2. First, the state list is initialized to the unvisited states; thus, the target state is initially excluded (Line 1). Then, all of the found paths by instantiations of 𝒫𝒞𝒜\mathcal{PCA} are gathered (Line 2). The fourth argument of 𝒫𝒞𝒜\mathcal{PCA} represents the found path that is initially empty. As already asserted, each successful backtracking step appends the found event to its incomplete path. At the end, the decision is made based on the path collection (Lines 3-7).

Algorithm 2 Reconfiguration Solvability Algorithm (𝒮𝒜\mathcal{RSA})
1:
2:qrq_{r} \triangleright Target state
3:qsq_{s} \triangleright Source state
4:RSUP \triangleright Supervisor
5:
6:solvability  
7:QTQRSUP{qr}Q_{T}\leftarrow Q_{\textbf{RSUP}}-\{q_{r}\}
8:𝒫𝒫𝒞𝒜(qr,qs,QT,)\mathcal{P}\leftarrow\mathcal{PCA}(q_{r},q_{s},Q_{T},\varnothing)
9:if 𝒫\mathcal{P}\neq\varnothing then
10:     return The reconfiguration problem IS solvable by                any path of 𝒫\mathcal{P}.
11:else
12:     return The reconfiguration problem IS NOT solvable.
13:end if

5 Example

We provide an example to illustrate a configuration problem associated with a DES.

Figure 4 depicts SMALL FACTORY (SF) with two 3-state machines M1 and M2, and buffers BUF1 and BUF2 with three slots and one slot, respectively. Assume that the machines can work with either of the buffers. In other words, SF has two modes: CSF1={M1,M2,BUF1}C^{1}_{\textbf{SF}}=\{\textbf{M1},\textbf{M2},\textbf{BUF1}\}, and CSF2={M1,M2,BUF2}C^{2}_{\textbf{SF}}=\{\textbf{M1},\textbf{M2},\textbf{BUF2}\}. Moreover, the events are described in Table 5. Given the required RS as Fig. 5, the synthesized RSUP is controllable including 78 states and 270 events.

Assume that SF resides currently at [41] 111In this section, symbols [q][q] and σ\Braket{\sigma} represent state qq and event σ\sigma, respectively. and a reconfiguration is requested to switch from CSF1C^{1}_{\textbf{SF}} to CSF2C^{2}_{\textbf{SF}}. Let [9] be the destination state, including 91\braket{91} where the reconfiguration event 91\braket{91} is defined.

Consequently, 𝒮𝒜\mathcal{RSA} backtracks from the [9] to [41] to find all forcible paths. The shortest path is 23,31,20,31,20,31\braket{23,31,20,31,20,31}, as depicted in Fig. 6. The path computation is analyzed as follows.

  • Backtracking [9] to [5]: according to BFC-2, backtracking is authorized; because 11\braket{11} can be disabled.

  • Backtracking [5] to [19]: 11\braket{11} can be safely disabled, but 22\braket{22} may occur sooner than 20\braket{20}, thereby preempting it according to BFC-3. According to the BFC-4, 23\braket{23} can be disabled, so the occurrence of 22\braket{22} is handled and blocked by the aforesaid disablement. Therefore, both paths 20\braket{20} and 22,23\braket{22,23} are qualified paths.

  • Backtracking [19] to [12]: the same as backtracking [9] to [5].

  • Backtracking [12] to [32]: the same as backtracking [5] to [19].

  • Backtracking [32] to [26]: according to BFC-1, backtracking is authorized; because there is no event competing with 31\braket{31} to occur.

  • Backtracking [26] to [41]: the same as backtracking [32] to [26], considering 23\braket{23} instead of 31\braket{31}.

Refer to caption
Figure 4: The schematic of SMALL FACTORY

The results demonstrate that the reconfiguration problem is solvable, and the supervisor can randomly select any path from the forcible path collection to realize the reconfiguration.

It is important to note, finally, that at state [9], which serves as source state for the RE 91\braket{91} the controllable event 11\braket{11} must be disabled, and 91\braket{91} must be forced to preempt the uncontrollable events 20,22\braket{20,22}. This is acceptable on physical grounds, inasmuch as 11\braket{11} (M1 takes a new workpiece) is controllable, and 20,22\braket{20,22} can only occur while M2 is working, so that preemption can be plausibly assumed to take place in the working time delay interval.

Note that the 2-way RS may result in blocking in case of retaining the possibility of a reconfiguration from CSF2C^{2}_{\textbf{SF}} back to CSF1C^{1}_{\textbf{SF}}, since disabling 91\braket{91} ends up with the disablement of another reconfiguration. We may address two approaches to solving this issue: first, CSF1C^{1}_{\textbf{SF}} can be considered as the initial state of RS, thereby solving the second reconfiguration problem independently of the first one; alternatively, a 1-way RS can be used for each reconfiguration.

Refer to caption
Figure 5: The RS corresponding to SMALL FACTORY
(the label v represents the event set {11,12,13,20,22,23,30,31,32,33}\{11,12,13,20,22,23,30,31,32,33\})
Table 1: Descriptions of SMALL FACTORY events
Event Description
11 M1 takes a workpiece.
20 M2 successfully completes processing a workpiece.
12 / 22 Breakdown occurs in M1 / M2.
13 / 23 M1 / M2 is repaired.
30 / 32 M1 increments BUF1 / BUF2.
31 / 33 M2 decrements BUF1 / BUF2.
91 The reconfiguration CG1CG2C^{1}_{\textbf{G}}\rightarrow C^{2}_{\textbf{G}} is requested.
93 The reconfiguration CG2CG1C^{2}_{\textbf{G}}\rightarrow C^{1}_{\textbf{G}} is requested.
Refer to caption
Figure 6: The forcible backtracking goes from [9] back to [41]

6 Conclusion

This paper proposes a solution to the reconfiguration problem for DES. To this purpose, we first model reconfiguration requirements of the DES by RS. Then, SCT synthesizes RSUP, considering the RS. Finally, forcible paths are computed by a dynamic-programming-based algorithm, so it can check the solvability of a user-initiated reconfiguration request. The algorithm in fact backtracks from a desired reconfiguration event source state to the current state in RSUP. Guaranteed finite reachability of the source state is confirmed (or otherwise) by the construction of the forcible path set.

Acknowledgment

This work is supported by the Natural Sciences and Engineering Research Council (NSERC), Grant Number DG-480599.

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