An Efficient NVM based Architecture for Intermittent Computing under Energy Constraints

The following activities occur in the system during a power failure and before initiating the backup procedure.

1. 1.

   Except for the processor, all system peripherals receive power-off signals.

2. 2.

   As the processor is stalled, no new instructions are carried out by the processor.

   1. (a)

      Since all peripherals are switched off, no peripheral can issue an interrupt during this time.

3. 3.

   Because the processor is stalled, it consumes no dynamic energy. As a result, we can use the entire capacitor energy to backup the volatile contents.

After completing the preceding three phases, we initiate the backup procedure. During backup, the volatile contents are stored in the register file and the SRAM-based cache; a specially designed controller is responsible for saving the volatile contents to STT-RAM-based BR at LLC. During backup, the controller reads the (set, way) fields in DBT and WBQ one entry after another to identify a block in the L1 cache, then writes the dirty data to the STT-RAM-based BR at LLC. The controller performs the following operations: reading from the register file, reading from the SRAM-based cache (‘K’ blocks data), and writing to STT-RAM-based BR at LLC. In the proposed architecture, the register file size and the number of dirty blocks at the L1 cache are minimal, and the backup procedure requires a constant and fixed number of cycles. As a result, the proposed architecture requires a fixed overhead for backup.

The processor has been set to shutdown mode once the backup procedure has been completed. We use the capacitor energy $(E_{capacitor})$ to perform the backup. When the power is resumed, we perform the same operations as in a conventional processor.

Therefore, for a given capacitor energy, system configuration, register files and read/write parameters for the memory system, we define the required number of $K$ blocks in section III-B using equation 3.

In order to reduce the system’s energy consumption, we first need to reduce the number of writes to both STT-RAM and PCM. We performed experiments to compare the number of writes for NVM in baseline and proposed architectures. All values shown in figures 3 and 4 are normalized with the baseline-1 architecture. All values shown in figure 5 are normalized with the baseline-3 architecture. Baseline-2 gets fewer writes than the proposed architecture at LLC and PCM by 14.11% and 7.84%, as shown in figure 3. Compared to baseline-1, the proposed gets 18.97% fewer writes at the LLC and 10.66% at the PCM, as shown in figure 3.

As shown in figure 4, the proposed architecture consumes 17.56% less energy than baseline-1 architecture and 4.93% more energy than baseline-2 architecture. Under a stable power supply scenario, the proposed architecture consumes less energy than baseline-1 and more energy than baseline-2.

During a power failure, the proposed architecture backup only the contents of DBT and WBQ to LLC. The combined size of DBT and WBQ is approximately less or equal to 4 KB. As a result, we compared the proposed architecture to baseline-3 to see how it performs in normal operations. As shown in figure 5, architecture-3 performs poorly compared to the proposed and baseline architectures. Compared to baseline-3, the proposed architecture takes 38.79% less execution time during regular operation. Thus, using a small L1 size cache doesn’t improve performance during a stable power supply.

As shown in figure 5, we compared architectures with LRW and LFW policies. As shown in table IV, the proposed architecture uses the LFW replacement policy, and the proposed using LRW architecture uses the LRW replacement policy instead of LFW. As shown in figure 5, the proposed architecture takes 13.11% less execution time than baseline-1 architecture and 5.10% more execution time than baseline-2 architecture. The proposed architecture with the LFW policy performs better than the architecture with the LRW policy.

We performed experiments to determine K, M, and N values as shown in the figures 6, 7. We performed the experiments for various $K$ values, as shown in figure 6. We performed experiments with various $K$ values from K=8 to K=128. For all experiments shown in figure 6, we assumed (M, N) to be equal. For example, if K=16, M=N=8. As shown in figure 6, increasing the $K$ value consumes higher energy values. We assume capacitor energy as input; thus, $K$ is also input to our design based on equation 3. We analyzed various $K$ values because different sizes of capacitors are available in the market. The size of $M$ entirely decides the LRW field’s size. Figure 7 already show the energy consumption values for various $M$ values. Based on the $M$ value, we can set the LRW field’s size. If we look at the figure 6, we observe that the system uses less energy up until K=42, then gradually consumes more energy as K increases.

As shown in figure 7, we used K as 32 in these experiments. Within K=32, we experimented on various (M, N) pairs. In figure 7, when M=2, N becomes 14 (16-M), and when M=12, N becomes 4. We performed experiments with various possible (M, N) pairs such as (6, 10), (16, 16), (24, 8), and (32, 0). We observe that (26, 6) utilizes less energy than the other pairs. As a result, for K=32, we used (M, N) as (26, 6) throughout this paper. In the same way, we experimented to identify the best (M, N) pair for K=64. We observe that (54, 10) uses less energy than all other pairs for K=64.

We performed experiments on the same benchmark suite used in section V-A to determine the K, M, and N values. We selected K, M, and N values based on the average values. The optimal K, M, and N values vary depending on the application behavior and the system configuration. We also observed that for the selected K, M, and N values, the majority of benchmarks (11 out of 14) outperform others. The variation between other K, M, and N values and selected values is negligible for the other three benchmarks. As a result, we selected K, M, and N values after considering all benchmarks. We have shown the overall average values in figures 6 and 7. Table I lists the selected K, M, and N values.

As shown in figure 1, our proposed architecture has four design alternatives. Using NVM at both L1 and LLC in architecture-1 gives us the third alternative. Adding BR to architecture-2 gives us the fourth alternative.

We performed experiments with the unified NVM architecture, i.e., architecture-3. We compared unified NVM architecture to the proposed architecture to determine how good or bad architecture-3 will perform under a stable power supply. We compared architecture-3 to architectures-1 and 2 for dynamic energy consumption, as shown in figure 8. Under a stable power supply, architecture-1 outperforms architectures-2, 3, and the proposed architecture. This advantage is due to the use of volatile memory at L1 and LLC in architecture-1.

We observed that NVM receives more read/write accesses when the entire memory at L1 is NVM-based. Compared to the proposed architecture, architecture-3 consumes 43.25% more energy and has a performance overhead of 38.99% under a stable power supply. This analysis motivated us to compare the proposed architecture with one that uses NVM-based memory for only DBT and WBQ at the L1 cache. The proposed architecture consumes 19.41% less energy than this design.

We performed experiments to compare architecture-3 with the architecture that uses NVM-based DBT and WBQ for the number of NVM writes, as shown in figure 9. Under a stable power, NVM-based DBT and WBQ design consumes 37.17% lesser writes than architecture-3 and 21.79% more writes than the proposed architecture. As a result, unified NVM architecture is not a good choice to use for regular operations.

Analysis with Different Checkpointing Approaches: The proposed backup/restore strategy looks similar to checkpointing. We performed experiments with a stable power supply to compare the proposed backup/restore strategy to existing checkpointing approaches. We used three different checkpointing methods for these experiments.

First, we designed a traditional checkpointing technique, introducing a safe point at every 4 million instructions. For every 4 million instructions, we backup the system state to NVM. We restore from the main memory at each safe point and continue with the application’s execution. Our proposed architecture outperforms traditional checkpointing because backup only occurs during power failure. All values shown in figures 10 and 11 are normalized with the traditional checkpointing technique. As shown in figures 10 and 11, the proposed architecture reduces performance overhead and energy consumption by 41.27% and 37.95%.

Second, we used a checkpointing method proposed by Xie et al. [16]. Xie et al. identified the important volatile blocks that needed to be backed up during a power failure using STT-RAM-based counters (DBCounter and MCounter). Xie et al. used the LRU policy for replacement in NVM-based caches and volatile caches. Updating and accessing these counters is similar to NVM writes and reads, which use more energy and slow down the system. Because Xie et al. performs backup during a power failure, we compared performance and energy consumption based on total NVM reads/writes. As shown in figures 10 and 11, the proposed architecture reduces performance overhead and energy by 19.03% and 14.72%.

Third, we implemented a checkpointing procedure that creates a checkpoint whenever the system state changes. For every write request, we increment the write counter (WC). Once WC reaches the threshold, the checkpoint procedure is triggered, size of the WC size is the same as the proposed system configuration. This checkpointing technique increases NVM reads/writes, degrades system performance, and consumes more energy. As shown in figures 10 and 11, the proposed architecture reduces performance overhead and energy consumption by 39.11% and 33.10%.

The traditional checkpointing technique is both the standard and the worst-case scenario for these intermittently powered systems. If we want to add another level of filtering checkpoints, we can add a counter per cache block, and if any cache block reaches the defined threshold, the checkpoint procedure is triggered. This checkpointing technique performs better than traditional checkpointing. However, the second checkpointing technique increases the number of NVM accesses. Instead of checkpointing at every safe point or for every $>WC$ case, we can add another level for reducing checkpoints by placing a checkpoint only during a power failure. Xie et al. proposed a checkpointing policy that only backups the dirty blocks selected during a power failure. Xie et al. outperform the other two checkpointing policies. However, the proposed backup strategy reduces performance overhead and energy consumption compared to Xie et al., as shown in figures 10 and 11.

We simulate frequent power failures by assuming that a power failure occurs for every 2 million instructions. The open-source version of the Gem5 core does not model an intermittent power supply processor. By introducing interrupts, we modified gem5 to support intermittent power supply processors. So, for every 2 million instructions, there is an interrupt, which the processor model admits as a power failure. The Gem5 simulator is used to run all of the experiments for one billion instructions. We assumed a power failure occurs for every 2 million instructions because, on average, 2 million instructions take approximately 25-30 ms of time to execute. In another way, there is a power interruption every 30 ms, so these power failures are not as frequent as they would be in real life. Therefore, the results are rather conservative.

Considering energy harvesting sources, such as piezoelectric and vibration-based sources, they extract significantly less energy from their surroundings. In such cases, the capacitor is unable to store sufficient energy, leading to frequent power failures. As a consequence, our proposed architecture is capable of handling these worst-case scenarios. However, existing work by Xie et al. [16] made similar assumptions that almost every power failure occurs every 200 and 500 ms.

All values shown in figures 12, 13 are normalized with baseline-2 architecture. The proposed architecture consumes 20.94% less energy than the baseline-2 architecture, as shown in figure 12. We evaluated the proposed architecture with both replacement policies. The architecture that uses LFW performs better than LRW, as shown in figure 13.

We performed a series of experiments to analyze the backup energy and the effect of PCM on our proposed architecture.

During frequent power failures, architecture-3 outperforms architecture-1 and the proposed architecture for backup energy consumption. Compared with architecture-1, architecture-4 consumes 35.57% less energy, as shown in figure 14. Because we need to backup the entire L1 and LLC to PCM, architecture-1 requires more backup energy than architecture-3. Due to the unified NVM architecture, architecture-3 only needs to backup volatile register contents. Architecture-4 requires constant backup energy because we only need to backup volatile register contents and $K$ blocks to BR during a power failure. Thus, architecture-4 consumes more energy than architecture-3. We have shown the required backup energy for architecture-1 and 4 in equation 1. Architectures-3 and 4 use constant energy to backup volatile contents.

We want to examine whether all these benefits are because of PCM at the main-memory level. So, we compare the energy consumption for four architectures shown in figure 15. As shown in figure 15, architecture-1 consumes more energy than the other three architectures because the number of writes to PCM is more in architecture-1. The only difference between architecture-2 and 4 is that architecture-4 is BR-enabled.

The performance of BR-enabled architecture is more effective than that of non-BR-enabled architecture, i.e., architecture-2. With a BR at LLC, we can directly place those $K$ blocks in BR and quickly restore the contents of the L1 cache. When we remove BR at LLC, we must first update in LLC. If LLC is full, we need to replace some blocks at LLC to make space for the L1 dirty blocks. We use the LRU replacement policy at LLC, which increases write to PCM compared to the BR-enabled architecture. We assume our system has a fixed-energy capacitor that can only backup the $K$ blocks and the register file. When we remove BR from LLC, the capacitor no longer supports safe backup because we have to lose $K$ or $<K$ blocks (either from L1 or LLC). As a result, we either end up with the wrong results or have to restart the application. As illustrated in figure 12, BR-enabled architecture consumes less energy than the architecture without BR at LLC. This benefit is because of the increased number of writes to PCM. The proposed architecture consumes less energy than the baseline-2 architecture because frequent power failures increase reads/writes to NVM, as shown in figure 12.

Compared with architecture-1, architecture-2 consumes 19.02% less energy, and architecture-4 consumes 32.64% less energy. Figure 15 shows that architecture-4 is better than the other three architectures. Therefore, not all of these improvements are solely linked to PCM since our proposed policies also help to achieve better performance and energy.

We performed experiments with the unified NVM architecture, i.e., architecture-3. All values shown in figure 15 are normalized with architecture-1. Under frequent power failures, architecture-3 outperforms architecture 1, but not architecture-2 and the proposed architecture. This advantage for architecture-3 is due to the usage of NVM at L1 and LLC.

Architecture-3 consumes 23.01% more energy than the proposed architecture, i.e., architecture-4, as shown in figure 15. This benefit for the proposed architecture is because the energy required for backing up the $K$ blocks is less than that of the energy required for architecture-3 during regular operations. Figures 8 and 9 show that architecture-3 consumes more energy and attracts more NVM reads and writes during regular operations. Architecture-3 is not suitable for intermittent power supply scenarios due to these overheads during normal operations. The unified NVM architecture requires additional procedures to make the system more energy efficient.

Analysis with Different Checkpointing Approaches: The proposed backup/restore strategy looks similar to checkpointing, a widely used approach to save the system state during a power failure. We performed experiments to compare the proposed backup/restore strategy with the existing checkpointing approaches under frequent power failures. For these experiments, we used four different checkpointing methods.

First, we designed a traditional checkpointing technique. Section V-C1 has discussed the checkpointing technique’s implementation details. All values shown in figures 16 and 17 are normalized with the traditional checkpointing technique. For example, suppose an unexpected power failure occurs at the $7th$ million instruction. We re-execute the application from the $4th$ million instruction because it is the closest safe point. These unnecessary executions increase NVM writes/reads, consume more energy, and degrade system performance. The proposed architecture reduces performance overhead and energy consumption by 48.70% and 40.19%, as shown in figures 16 and 17.

Second, we used a checkpointing method proposed by Xie et al. [16]. The implementation details of the Xie et al. checkpointing technique are discussed in section V-C1. The proposed architecture reduces performance overhead and energy consumption by 27.99% and 20.07%, as shown in figures 16 and 17. This advantage is due to the author’s selection of an LRU-based replacement policy for updating the counters, which we observed as insufficient to reduce the number of writes to NVM. Another reason is that Xie et al. did not backup the entire dirty block to NVM, which requires the application to be re-executed, which consumes more energy during frequent power failures.

Third, we implemented a checkpointing procedure that creates a checkpoint whenever the system state changes. Section V-C1 has discussed the checkpointing technique’s implementation details. The proposed architecture reduces performance overhead and energy consumption by 38.71% and 32.13%, as shown in figures 16 and 17. During frequent power failures, backup/restore sizes increase in this technique, potentially causing NVM reads and writes to increase, which degrades system performance and consumes more energy.

Fourth, we implemented a checkpointing procedure that initiates a backup procedure whenever the system state changes. During a power failure, the checkpoint procedure is triggered, and we compare the previous checkpoint data to the new checkpoint data, block by block. Only the volatile contents that differ from the previous checkpoint data are backed up. Copy-by-Change checkpointing procedures are proposed by S. Ahmed et al. [23, 24]. The proposed architecture reduces performance overhead and energy consumption by 21.93% and 16.55%, as shown in figures 16 and 17.

We already discussed the first three checkpointing policies in section V-C1. In order to add another level to Xie et al. for reducing the checkpointing overhead. Instead of checkpointing all cache blocks, S. Ahmed et al. policy checks and compares the most recently checkpointed data. When compared to Xie et al., this policy reduces NVM accesses; thus, the S. Ahmed et al. checkpointing policy outperforms the Xie et al. policy. However, accessing and comparing NVM-based previous checkpointed data also induces reads/writes to NVM. Figures 16 and 17 show that the proposed backup strategy performs better than the existing checkpointing techniques.

We compared the average memory access time (AMAT) for two architectures. One, the architecture is without any proposed data structures and replacement policies, i.e., the baseline-2 architecture. Second, the architecture with proposed data structures and replacement policies. We performed these experiments to analyze the proposed architecture to see how the proposed data structures and replacement policy impacted system performance. AMAT analysis allows us to determine which of the two architectures is faster during frequent power failures. The proposed architecture outperforms the baseline-2 architecture by 19.61% during frequent power failures. This advantage is due to DBT and WBQ; most L1 requests result in hits, which reduces performance overhead. Another significant advantage of the proposed architecture is the explored replacement policies. During a stable power supply, the proposed replacement policy helps in saving important blocks (write-intensive blocks) at the L1 cache rather than evicting them. Thus, incorporating DBT and WBQ improves the proposed architecture’s performance under intermittent power.