A N-Path Receiver With Harmonic Response Suppression

A switched-capacitor N-path circuit[1] can be employed for filtering an RF signal as well as a passive downconverter. Switch-based implementations of such filters have been demonstrated in recent literature, e.g., [2]. N-path filters can provide a high effective quality factor, a high dynamic range and a tunable response, in addition to being scalable with process technology [3].

A known limitation of a switch-based N-path filter is that in addition to downconverting signals around the desired center frequency, the circuit also downconverts signals located around harmonics of the center frequency. An approach to reduce the harmonic response employing a PWM representation of a sinusoidal clock was shown in [4]. An N-path filter with a fundamental response at $f_{LO}$ that employs rectangular clocks requires a primary clock frequency of $Nf_{LO}$. With PWM clocks, the primary clock frequency is $MNf_{LO}$, where the degree of harmonic suppression improves with increasing $M$. For $N=4$ and $M=4$, the approach effectively removes harmonic response up to nearly $8\times f_{\text{{LO}}}$ as shown in [4]. A challenge of the approach is the requirement for high PWM clock frequency, which can limit the achievable harmonic suppression due to narrow pulse-widths.

Mixer-first receivers that provide cancellation of LO harmonic responses at the receiver output have been demonstrated in prior literature [5, 6, 7]. The goal of this work is to provide harmonic response suppression at the input of the N-path filter, similar to [4], without the requirement for high clock frequency. A frequency-translation feedback loop is used in the proposed approach. The use of a frequency-translation loop for input matching and enhancing out-of-band blocker performance near the fundamental LO frequency of a receiver was shown in [8]. Feedback-based interference-rejection in a broadband channelizer using reconfigurable harmonic rejection mixers in the feedforward and feedback paths for suppression of harmonic LO levels was described in [9].

In this work, an eight-phase, N-path receiver that suppresses the response around the $3^{\text{rd}}$ and the $5^{\text{\text{th}}}$ harmonics of the fundamental LO frequency, $f_{LO}$, at the RF input is proposed. The design employs capacitive baseband loads. The N-path filter by itself provides a bandpass response at the fundamental LO frequency and all odd harmonics of the LO, with bandwidth determined by the baseband capacitors and the source resistance [10].

In order to suppress the input response from the harmonics of the LO, the baseband signal components downconverted by the $3^{\text{rd}}$ and the $5^{\text{\text{th}}}$ harmonics of the LO signal at the output of the N-path filter, are upconverted in a harmonic-selective feedback path to the input. The feedback path operates only around the $3^{\text{rd}}$ and the $5^{\text{\text{th}}}$ harmonics. This is ensured by using a baseband harmonic selective combiner, that selects only these signal components, and rejects the signal downconverted by the fundamental $f_{LO}$. In addition, the feedback path upconverter employs a pulse-width-modulated LO (PWM-LO) with an ideally zero component around $f_{LO}$ and primary harmonics at $3f_{LO}$ and $5f_{LO}$ [11][12] as described below.

Suppressing the harmonic response at the RF input also ensures similar suppression at the baseband output. Combined with another baseband harmonic rejection stage which selects baseband signals downconverted from the fundamental, the architecture is shown to provide harmonic rejection of nearly a two-stage harmonic rejection downconverter [13][14]. The filter response at $8kf_{LO}\pm f_{LO}$ is not mitigated by the architecture, for $k\geq 1$, however it assumed that the inherent attenuation provided by the N-path filter at baseband is adequate.

The architecture is described in Section II. An approach for avoiding the frequency-shift in the response caused by a parasitic input capacitance [15] is also described. Section III describes simulation-based results and the conclusion follows in Section IV.

The receiver architecture is shown in Fig. 1. The architecture consists of a main-loop, which provides the N-path filtering at the input, and the baseband signals, and two harmonic rejection combiners, one within the loop (HR2), and one outside the loop (HR1). HR1 selects signals downconverted around $f_{LO}$, while HR2 selects signals dowconverted from around $3f_{LO}$ and $5f_{LO}.$ The design of these is described below.

Simulations of the proposed architecture of Fig. 1 are shown below. The design is simulated and verified using a 65-nm commercial CMOS process, which includes the complete device model. The design employs an 8-phase clock with $f_{LO}$ = 500 MHz. The harmonic responses at the baseband of an N-path filter by itself, and for the main-loop shown in Fig. 1 are shown in Fig. 6. The input frequency is swept from 300 MHz - 3 GHz and the frequency-translated output at baseband is observed. The baseband components downconverted from $3f_{LO}$ and $5f_{LO}$ can be seen to be reduced to nearly 20 and 25 dB relative to the component from $f_{LO}$, respectively, with the feedback loop, compared to approximately 3 dB and 6 dB respectively for the N-path filter by itself.

The RF response for the above two cases is compared in Fig. 7. The default N-path filter exhibits downconversion from all odd harmonics of $f_{LO}$, while the main-loop shows a response only at $f_{LO}$, and thus resembles an ideal BPF. The floor of the response is set by the switch resistance.

Harmonic rejection at the $3^{\text{rd}}$ and the $5^{\text{\text{th}}}$ harmonics is shown in Fig. 8. The proposed architecture has effectively a second-order harmonic rejection at the $3^{\text{rd}}$ and the $5^{\text{\text{th}}}$ harmonics, where as the combination of the N-path with HR1 has only first-order harmonic rejection. The second-order harmonic rejection is due to the suppression of the $3^{\text{rd}}$ and the $5^{\text{\text{th}}}$ harmonics at the input of the N-path filter. A total harmonic rejection of approximately 50-60 dB is observed in the proposed architecture.

Simulated noise figure and S11 at $f_{LO}=500$ MHz are 6.5 dB and -15 dB respectively. The 3-dB blocker compression point, B3dB, is simulated by observing the blocker level around $3f_{LO}$ and $5f_{LO}$ which reduces the small-signal gain at $f_{LO}$ at the output of HR1 by 3dB. For the proposed architecture the B3dB resulting from the $3^{\text{rd}}$ and the $5^{\text{\text{th}}}$ harmonics of $f_{LO}$ is +2.1 dBm and +8.4 dBm respectively. The B3dB for N-path + HR1, without the feedback loop, is -6.5 dBm and -3.4 dBm respectively.

A harmonic suppressing N-path filter that employs a a harmonic selective combiner in the feedback path with a PWM-LO based upconverter is proposed. A baseband harmonic combiner is employed with the feedback loop at the output of the N-path filter, to select the desired signal from the input spectrum. The HRM in the feedback generates the $3^{\text{rd}}$ and the $5^{\text{\text{th}}}$ harmonics responses, which effectively attenuates the harmonic responses observed at these frequencies at the input of the N-path filter. Due to this attenuation, the design operates as a second-order harmonic-rejection downconverter. Simulation results using commercial 65-nm CMOS devices are presented.