A Compact Readout Electronics Based on Current Amplifier for Micromegas Detector
in Muon Imaging

The architecture of the scalable readout electronics system used in this paper is shown in Figure 3. It comprises highly integrated front-end electronic (FEE) boards, a data acquisition (DAQ) board, and a PC. Each FEE board amplifies and digitizes detector signals, and transmits these data to the DAQ board via an optical fiber link running at 200 Mbps. The DAQ board processes and aggregates the data from multiple FEE boards and sends them to the PC via a USB 3.0 link at a rate up to 190 MB/s for final processing and storage. The DAQ board is a generic back-end board designed in our laboratory for various applications, including muon imaging experiments [19]. With this structure, this paper presents the FEE board built with six ADAS1128 chips and demonstrates its ability to acquire signals from Micromegas detectors.

The FEE adopts the current readout chip ADAS1128 [20] designed by ADI. A simplified internal structure of this device is shown in Figure 4. The chip is composed of 128 current integration amplifiers, sample circuits, two 24-bit resolution analog-to-digital converters (ADCs), a data processing part, and two 24-bit configuration registers. Each input current signal is integrated by an integrating amplifier and sampled by a sample circuit. The output signal is fed to the built-in ADCs for analog-to-digital conversion. The digital code values output from the ADCs are transmitted through the Low-Voltage Differential Signaling (LVDS) serial interface.

The integration time can be flexibly configured from 50.7 $\mu$s to 900 $\mu$s. The dynamic range is related to the sampling rate and the gain of the integrator. As a current-to-digital readout chip, the integration time of the ADAS1128 is the same as the readout cycle time. The adjustable dynamic range is -660.17 fC to 32.23 pC when the integration time is 50.7 $\mu$s. The dynamic range and the integration time are configurable via a 4-wire serial peripheral interface (SPI). Moreover, The chip is mounted in a 1 cm $\times$ 1 cm BGA (Ball Grid Array) package and has a power consumption of 4.5 mW per channel.

After power-up, the built-in automatic procedure for calibrating the gain and offset of the 128 measurement channels can be initiated via SPI. The chip then operates in continuous acquisition mode, integrating all charge signals during the specific integration time. Once a single integration cycle is completed, a new integration cycle begins. The conversion results for the 128 channels from the previous cycle (N) are output in the second subsequent integration cycle (N+2). Thus, this chip operates without dead time and charge loss.

To read out Micromegas detectors for muon imaging, the integration time of the chip is set to 50.7 $\mu$s (the shortest integration time) to prevent recording more than one muon event within an integration time window. According to the manufacturer’s datasheet, the inherent noise of the chip increases when the dynamic range is increased while the integration time remains fixed. Therefore, the dynamic range of the chip is set to -77.97 fC to 0 fC (ADC code values from 0 to 16383) to cover the signal range of the detector while meeting the low noise readout requirement.

The FEE consists of a ready-to-use module (core board) and a base board, as shown in Figure 5. The core board and the base board are interconnected via four 0.8 mm-pitch connectors. The core board has an FPGA (Artix-7 200T from Xilinx), onboard power modules, a double data rate synchronous dynamic random access memory, a quad serial peripheral interface flash, a 50 MHz crystal oscillator, and power management chips.

The base board uses 6 ADAS1128 chips, providing 768 input channels for reading Micromegas signals. For each channel, an Electro-Static Discharge (ESD) protection circuit is designed. The detector signals are integrated and converted to digital format within the ADAS1128 chip. The FPGA processes the data from the six ADAS1128s and transfers them via the communication interface as required. The communication interfaces of the baseboard comprise an optical transceiver and a USB 3.0 port. The optical fiber circuit is designed with a Clock and Data Recovery (CDR) chip, ADN2817, which can retrieve clock and serial data from the optical fiber link. The USB 3.0 circuit uses the CYUSB3014 chip designed by Cypress, facilitating single-board test.

The number of fired detector strips for one cosmic-ray muon event typically ranges from about 2 to 10 in one direction. Based on test results, the maximum number of fired strips for a single muon event is 25. The data amount for a single muon event in one FEE board unit is approximately 150 bytes (50$\times$24 bits).

The back-end electronics utilize the previously designed DAQ board shown in Figure 6. It consists of a main board and an extension board (following the terms used on Figure 6). The extension board is connected to the main board through the FPGA Mezzanine Card (FMC) interface. The main board uses an FPGA as the main control chip, which is mainly responsible for FEE configuration, data aggregation, clock distribution, and trigger elaboration. The extension board provides 32 optical fiber links for connecting FEE boards and offers various connectors for other external devices.

The DAQ board communicates with FEE boards via optical fibers using a custom protocol, as shown in Figure 7. The DAQ board sends the global reference clock of the system and configuration data with Direct Current (DC) balanced encoding to FEE, and FEE retrieves the original clock and data from the serial stream using a CDR chip. The original clock is processed by one of the internal Mixed-Mode Clock Managers (MMCMs) of the FPGA to produce the system clock. Data that have been time-multiplexed for transmission are split into trigger signals and configuration commands at the FEE end.

The FEE generates “pre-trigger” signals and acquisition data, which are encoded and transmitted to the DAQ board over the same optical fiber. Since the clock source corresponding to the data stream is synchronized with the DAQ board, the DAQ board can catch the data with phase adjustment through FPGA logic.

The electronics can operate in two trigger modes: self-trigger and external-trigger. In external-trigger mode, the DAQ board receives a trigger pulse from another system and sends it to the FEE boards. The FEE boards then transmit the data to the DAQ board.

In self-trigger mode, the system will judge whether a valid muon is detected. The schematic design of the self-trigger is shown in Figure 8. When a single chip detects that the signals from at least any two channels exceed a pre-defined threshold, the over-threshold flag signal of the chip is set to 1; otherwise, it remains at 0. After all the data of one acquisition period are judged, each FEE sends a ”pre-trigger” word composed of 6 hit bits (one hit bit per ADAS1128 chip) to the DAQ board.

The DAQ board combines the pre-trigger words of all FEE boards using FPGA logic to produce the valid trigger. Firstly, it checks if there are hits in both the X and Y directions of the detector corresponding to each FEE. Then, it counts the number of hits in the X and Y directions of the whole system and tests if these exceed preset values. If the counts exceed the preset values, the DAQ board sends a trigger together with the trigger ID to all FEE boards.

Our muon imaging system prototype consists of 6 layers of Micromegas detectors, 6 FEE boards, a DAQ board, a host computer, and high-voltage modules, as shown in Figure 9. Each FEE is connected to a 15 cm $\times$ 15 cm Micromegas detector through flexible printed circuit boards, and they are integrated in a single module. The entire system operates in self-trigger mode. The readout strips of each detector are grounded via 1 M$\Omega$ resistors, and the mesh voltage and drift electrode voltage are set to -550 V and -678 V, respectively. With this configuration, the gain of detectors is greater than 10⁴[11].

In the channel response linearity test, the voltage signal generated by an external generator is converted to a charge signal by generating a step-down signal and sending it to a 1pF (5% precision) capacitor in series. The gain and performance of 128 channels from one FEE are presented in Figure 10. The integral non-linearity is 2.8%.

The noise test is performed on FEE by recording the pedestal while the detector is connected. Figure 11 shows the statistics of the equivalent input noise charge for all channels, with 95% of the channels of the 6 ADAS1128 chips (768 channels) having a noise of less than 1.22 fC.

The detector energy resolution tests are performed using a ${}^{55}\textnormal{Fe}$ radioactive source. The energy spectrum and hit diagram are shown in Figure 12(a) and Figure 12(b) respectively. The peak position of the full energy peak is obtained by Gaussian fitting to be about 389.3 fC, and the energy resolution is 20.23% FWHM (Full Width at Half Maximum) at 5.9 keV. The results of the energy resolution tests are consistent with the previous result [16].

There are shaded areas in the hit diagram, caused by the hot melt adhesive pads between the detector resistive electrode and the mesh electrode. These pads block the downward drifting electrons, preventing the electrons from drifting into the avalanche region. As a result, no inductive signal can be generated in this region.

Each cosmic ray muon will deposit energy in the drift area, generating induction signals on the readout strips in both the X and Y directions. The charge in each direction is obtained by summing up the charges on the detector strips corresponding to the reconstructed hit positions. Subsequently, the charges from the two directions are summed to obtain the cosmic ray energy deposition spectrum, as shown in Figure 13. From the energy spectrum, the charge distribution mainly follows the expected Landau distribution. After performing a Landau-Gaussian convolution fit using ROOT, the peak value is approximately 149.94 fC.

The method for calculating the spatial resolution of the muon track system is shown in Figure 14, with an example of calculating the spatial resolution of the i-layer. By using the hit positions of the other five layers as the reference track, the fitted hit position x${}_{i_{fit}}$ can be obtained, where x${}_{i_{fit}}$ is calculated by (1-3). Then, the offset $\Delta x_{i}$ was defined by (4). By statistically analyzing a large number of muon tracks, the distribution of $\Delta x_{i}$ is obtained, and the standard deviation $\sigma$ ($\Delta x_{i}$) of the distribution is the spatial resolution of the layer detector.

The spatial resolution of the Micromegas detector in the X and Y directions is shown in Figure 15. When calculating instances from different angles separately, the uncertainty in the initial ionization position increases as the incident angle of the muon increases. For 0 $\sim$ 5^∘ incident muons, the spatial resolution of the detector is better than 200 $\mu$m. In the detector anode PCB (Printed Circuit Board), X direction readout strips are located above the Y direction, and X direction readout strips can collect more charge. Therefore, the spatial resolution in the X direction is slightly better than in the Y direction.

The detection efficiency is defined as the ratio of effective events recorded by the target detector (i-layer) to coincidence events of the reference tracker (the remaining five layers of detectors), where the effective events of the target detector are selected with the condition that $\Delta x_{i}<10\times\sigma$ ($\Delta x_{i})$. The detection efficiency in the X and Y directions of detectors is shown in Table I. Results show that the efficiency of most of the 6-layer Micromegas detectors is over 95%.

Figure 16 shows the results of imaging blocks of tungsten (2 cm wide and 4 cm thick) placed on a carrier platform to form the letter $\mu$. After accumulating 24 hours of data, the imaging result was reconstructed using the Point of Closest Approach (PoCA) algorithm incorporating the k-Nearest Neighbors (k-NN) algorithm[8]. The reconstructed image shown in Figure 16(b) shows that our muon imaging system prototype can reconstruct the boundaries of the objects used in this test.